PowerPC 740 and PowerPC 750 Microprocessor Datasheet - IBM

PowerPC 740 and PowerPC 750 MicroprocessorCMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2L2 Bus Input AC SpecificationsSome specifications are shown in the following table as a Function of Maximum Core Frequency (Fmax).These specifications refer to the effective Fmax of the part after derating for application conditions. For example,a nominal 450 MHz part running at application conditions that derate its Fmax to 400 MHz will meet orexceed the specifications shown for Fmax = 400 MHz.L2 Bus Input Interface AC Timing SpecificationsSee ”Recommended Operating Conditions,” on page 11, for operating conditions.Num Characteristic Min Max Unit Notes29,30 L2SYNC_IN rise and fall time — 1.0 ns 2, 324 Data and parity input setup to L2SYNC_IN, Fmax upthrough 375 MHz.24 Data and parity input setup to L2SYNC_IN, Fmax = 400MHz.24 Data and parity input setup to L2SYNC_IN, Fmax = 433 and450 MHz.24 Data and parity input setup to L2SYNC_IN, Fmax = 466 andabove.1.5 — ns 11.4 — ns 11.1 — ns 11.0 — ns 125 L2SYNC_IN to data and parity input hold 0.5 — ns 1Note:1. All input specifications are measured from the Vm of the signal in question to the Vm of the rising edge of the input L2SYNC_IN. Input timings aremeasured at the pins (see Figure 8).2. Rise and fall times for the L2SYNC_IN input are measured from 0.5 to 1.5V.3. Guaranteed by design and characterization, and not tested.Figure 8. L2 Bus Input Timing Diagrams29 30L2SYNC_INVM2425ALL INPUTSVMVMVm = 1.4 V for L2OV DD = 3.3 V., else Vm = L2OV DD /29/6/2002 Version 2.0 Page 22