chapter 8.pdf

Section 8.2 Latches and Flip-Flops 571DO NOT COPY74LS0474LS04push SWSW_LDSW(a)DO NOTSW_LSWCOPYVDO NOTOH pushSWV OLCOPYGNDfirst contact(b)bounceV OHSW_LVDOOLFigure 8-5GNDSwitch input usingNOT COPY1a bistable forDSW0debouncingAdvantages of this circuit compared to other debouncing approaches arethatDOit has a low chip countNOT(one-third of a 74LS04), no pull-upCOPYresistors arerequired, and both polarities of the input signal (active-high and active-low)are produced. In situations where momentarily shorting gate outputs must beavoided, a similar circuit can be designed using a S-R latch and pull-up resistors,as suggested in Figure 8-6.DO NOT COPY+5 VFigure 8-6Switch input using74LS00an S-R latch forSWU_LDO NOTDSW_L debouncing.COPYpush+5 VDSWSWD_LDO NOT COPYWHERE WIMPY The circuit in Figure 8-5, while elegant, should not be used with high-speed CMOSWORKS WELL devices, like the 74ACT04, whose outputs are capable of sourcing large amounts ofDOcurrentNOTin the HIGH state. While shortingCOPYsuch outputs to ground momentarily willnot cause any damage, it will generate a noise pulse on power and ground signals thatmay trigger improper operation of the circuit elsewhere. The debouncing circuit inthe figure works well with wimpy logic families like HCT and LS-TTL.Copyright © 1999 by John F. WakerlyCopying Prohibited