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576 Chapter 8 Sequential Logic Design PracticesDO NOTHigh pin-count surface-mountCOPYpackaging supports even wider registers,drivers, and transceivers. Most common are 16-bit devices, but there are alsodevices with 18 bits (for byte parity) and 32 bits. Also, the larger packages canoffer more control functions, such as clear, clock enable, multiple outputDOenables,NOTand even a choice of latchingCOPYvs. registered behavior all in one device.8.2.6 Registers and Latches in ABEL and PLDsAs we showed in Section 7.11, registers are very easy to specify in ABEL. Forexample, Table 7-33 on page 543 showed an ABEL program for an 8-bit registerDOwithNOTenable. Obviously, ABEL allowsCOPYthe functions performed at the D inputs ofregister to be customized in almost any way desired, limited only by the numberof inputs and product terms in the targeted PLD. We describe sequential PLDsin Section 8.3.With most sequential PLDs, few if any customizations can be applied to aDOregister’sNOTclock input (e.g, polarity choice)COPYor to the asynchronous inputs (e.g.,different preset conditions for different bits). However, ABEL does provideappropriate syntax to apply these customizations in devices that support them, asdescribed in Section 7.11.1.Very few PLDs have latches built in; edge-triggered registers are muchDOmoreNOTcommon, and generally more useful.COPYHowever, you can also synthesize alatch using combinational logic and feedback. For example, the excitation equationfor an S-R latch isQ∗ = S + R′⋅QDOThus,NOTyou could build an S-R latchCOPYusing one combinational output of a PLD,using the ABEL equation “Q = S # !R & Q.” Furthermore, the S and R signalsabove could be replaced with more complex logic functions of the PLD’s inputs,limited only by the availability of product terms (seven per output in a 16V8Cor 16L8) to realize the final excitation equation. The feedback loop can beDOcreatedNOTonly when Q is assigned to aCOPYbidirectional pin (in a 16V8C or 16L8, pinsIO2–IO7, not O1 or O8). Also, the output pin must be continuously outputenabled;otherwise, the feedback loop would be broken and the latch’s state lost.Probably the handiest latch to build out of a combinational PLD is a Dlatch. The basic excitation equation for a D latch isDO NOT COPYQ∗ = C ⋅ D + C′⋅QHowever, we showed in Section 7.10.1 that this equation contains a static hazard,and the corresponding circuit does not latch data reliably. To build a reliableD latch, we must include a consensus term in the excitation equation:DO NOTQ∗ = C ⋅ DCOPY+ C′⋅Q + D ⋅ QThe D input in this equation may be replaced with a more complicated expression,but the equation’s structure remains the same:Q∗ = C ⋅ expression + C′⋅Q + expression ⋅ QCopyright © 1999 by John F. WakerlyCopying Prohibited
Section 8.2 Latches and Flip-Flops 577DO NOT COPYABUS ADDR1 ADDR2AVALIDDOREAD_LNOT COPYROMCS_LFigure 8-14Timing diagram for aDBUS DATA1 DATA2 microprocessor readDOfrom ROMNOTfrom a different deviceCOPYoperation.It is also possible to use a more complex expression for the C input, as weshowed in Section 7.10.1. In any case, it is very important for the consensus termto be included in the PLD realization. The compiler can work against you in thiscase,DOsince its minimizationNOTstep will find that the consensusCOPYterm is redundantand remove it.Some versions of the ABEL compiler let you prevent elimination ofconsensus terms by including a keyword “retain” in the property list of the retain propertyistype declaration for any output which is not to be minimized. In otherDO NOT COPYversions, your only choice is to turn off minimization for the entire design.Probably the most common use of a PLD-based latch is to simultaneouslydecode and latch addresses in order to select memory and I/O devices in microprocessorsystems. Figure 8-14 is a timing diagram for this function in a typicalsystem.DOThe microprocessorNOTselects a device and a location withinCOPYthe device byplacing an address on its address bus (ABUS) and asserting an “address valid”signal (AVALID). A short time later, it asserts a read signal (READ_L), and theselected device responds by placing data on the data bus (DBUS).Notice that the address does not stay valid on ABUS for the entire operation.DOThe microprocessor busNOTprotocol expects the address toCOPYbe latched usingAVALID as an enable, then decoded, as shown in Figure 8-15. The decoderselects different devices to be enabled or “chip-selected” according to the highorderbits of the address (the 12 high-order bits in this example). The low-orderbits are used to address individual locations of a selected device.DO NOT COPY32-bit latchdecoderto individual Figure 8-15device MicroprocessorQ[31:20]chip-select address latching andinputsDO NOT COPYdecoding circuit.ABUS[31:0] D[31:0]to deviceQ[19:0]addressAVALID GinputsCopyright © 1999 by John F. WakerlyCopying Prohibited
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References 687DOAs we mentioned in
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Exercises 6938.54DOModify the ABEL
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Exercises 695DO NOT COPYSYNCINASYNC
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