chapter 8.pdf

566 Chapter 8 Sequential Logic Design PracticesDO NOT COPYNOTHING’S In reality, there’s no such thing as a perfect clock signal. One imperfection that mostPERFECT designers of high-speed digital circuits have to deal with is “clock skew.” As weshow in Section 8.8.1, a given clock edge arrives at different circuit inputs at differentDO NOTtimes because of differences in wiringCOPYdelays, loading, and other effects.Another imperfection, a bit beyond the scope of this text, is “clock jitter.” A10-MHz clock does not have a period of exactly 100 ns on every cycle—it may be100.05 ns in one cycle, and 99.95 ns in the next. This is not a big deal in such a slowcircuit, but in a 500-MHz circuit, the same 0.1 ns of jitter eats up 5% of the 2-nsDOtimingNOTbudget. And the jitter in some clockCOPYsources is even higher!The other signals in Figure 8-2 may be flip-flop outputs, combinationaloutputs, or flip-flop inputs. Shading is used to indicate “don’t-care” signalvalues; cross-hatching as in Figure 8-1 on the preceding page could be usedDO NOT COPYinstead. All of the signals are shown to change immediately after the clock edge.In reality, the outputs change sometime later, and inputs may change just barelybefore the next clock edge. However, “lining up” everything on the clock edgeallows the timing diagram to display more clearly which functions areDOperformedNOTduring each clock period.COPYSignals that are lined up with the clock aresimply understood to change sometime after the clock edge, with timing thatmeets the setup- and hold-time requirements of the circuit. Many timingdiagrams of this type appear in this chapter.Table 8-1 shows manufacturer’s timing parameters for commonly usedDOflip-flops,NOTregisters, and latches in CMOSCOPYand TTL. “Typical” values are forTable 8-1 Propagation delay in ns of selected CMOS flip-flops, registers, and latches.74HCT 74AHCT 74FCT 74LSPart Parameter Typ. Max. Typ. Max. Min. Max. Typ. Max.DO NOT COPY’74 t pd , CLK↑ to Q or Q 35 44 6.3 10 25 40t pd , PR↓ or CLR↓ to Q or Q 40 50 8.1 13 25 40tDOs , D to CLK↑ 12 15 5 20t h , D from CLK↑ 3 3 0 5t rec , CLK↑ from PR↑ orNOTCLR↑ 6 8COPY3.5t w , CLK low or high 18 23 5 25t w , PR or CLR low 16 20 5 25’174 tDOpd , CLK↑ to Q 40 50 6.3 10 21 30t pd , CLR↓ to Q 44 55 8.1 13 23 35t s , D to CLK↑NOT16 20COPY5 20t h , D from CLK↑ 5 5 0 5t rec , CLK↑ from CLR↑ 12 15 3.5 25t w , CLK low or high 20 25 5 20t w , CLR low 25 31 5 20Copyright © 1999 by John F. WakerlyCopying Prohibited