chapter 8.pdf

610 Chapter 8 Sequential Logic Design PracticesDO8.4.6NOTCounters in VHDLCOPYLike ABEL, VHDL allows counters to be specified fairly easily. The biggestchallenge in VHDL, with its strong type checking, is to get all of the signal typesdefined correctly and consistently.DO NOTTable 8-14 is a VHDL programCOPYfor a 74x163-like binary counter. Noticethat the program uses the IEEE.std_logic_arith.all library, which includesthe UNSIGNED type, as we described in Section 5.9.6 on page 389. This libraryincludes definitions of “+” and “-” operators that perform unsigned addition andsubtraction on UNSIGNED operands. The counter program declares the counterDOinputNOTand output as UNSIGNED vectorsCOPYand uses “+” to increment the countervalue as required.In the program, we defined an internal signal IQ to hold the counter value.We could have used Q directly, but then we’d have to declare its port type asbuffer rather than out. Also, we could have defined the type of ports D and Q toDObe STD_LOGIC_VECTOR,NOTbut then weCOPYwould have to perform type conversionsinside the body of the process (see Exercise 8.33).Table 8-14 VHDL program for a 74x163-like 4-bit binary counter.DOlibraryNOTIEEE;COPYuse IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;entity V74x163 isDO NOTport ( CLK, CLR_L, LD_L, ENP,COPYENT: in STD_LOGIC;D: in UNSIGNED (3 downto 0);Q: out UNSIGNED (3 downto 0);RCO: out STD_LOGIC );end V74x163;DOarchitectureNOTV74x163_arch of V74x163COPYissignal IQ: UNSIGNED (3 downto 0);beginprocess (CLK, ENT, IQ)beginif (CLK'event and CLK='1') thenDO NOTif CLR_L='0' then IQ '0');elsif LD_L='0' then IQ