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596 Chapter 8 Sequential Logic Design PracticesDO NOT COPYQQ0CLKTQDO NOT COPYQQ1TQQQ2TDO NOT COPYQFigure 8-27A 4-bit binaryQQ3Tripple counter.QDO NOT COPYn-bit binary counter Probably the most commonly used counter type is an n-bit binary counter.Such a counter has n flip-flops and has 2 n states, which are visited in thesequence 0, 1, 2, … , 2 n −1, 0, 1, … . Each of these states is encoded as thecorresponding n-bit binary integer.DO NOT COPY8.4.1 Ripple CountersAn n-bit binary counter can be constructed with just n flip-flops and no othercomponents, for any value of n. Figure 8-27 shows such a counter for n = 4.Recall that a T flip-flop changes state (toggles) on every rising edge of its clockDO NOT COPYinput. Thus, each bit of the counter toggles if and only if the immediatelypreceding bit changes from 1 to 0. This corresponds to a normal binary countingsequence—when a particular bit changes from 1 to 0, it generates a carry to theripple counter next most significant bit. The counter is called a ripple counter because the carryDOinformationNOTripples from the less significantCOPYbits to the more significant bits, onebit at a time.8.4.2 Synchronous CountersAlthough a ripple counter requires fewer components than any other type ofDObinaryNOTcounter, it does so at a price—itCOPYis slower than any other type of binarycounter. In the worst case, when the most significant bit must change, the outputis not valid until time n ⋅ t TQ after the rising edge of CLK, where t TQ is thepropagation delay from input to output of a T flip-flop.synchronous counter A synchronous counter connects all of its flip-flop clock inputs to the sameDOcommonNOTCLK signal, so that all of theCOPYflip-flop outputs change at the same time,after only t TQ ns of delay. As shown in Figure 8-28, this requires the use ofT flip-flops with enable inputs; the output toggles on the rising edge of T if andonly if EN is asserted. Combinational logic on the EN inputs determines which,if any, flip-flops toggle on each rising edge of T.Copyright © 1999 by John F. WakerlyCopying Prohibited
Section 8.4 Counters 597DO NOT COPYCNTENEN Q Q0CLKTDO NOTEN Q Q1COPYTEN Q Q2DO NOTTCOPYFigure 8-28EN Q Q3 A synchronous 4-bitbinary counter withTserial enable logic.DO NOT COPYAs shown in Figure 8-28, it is also possible to provide a master countenablesignal CNTEN. Each T flip-flop toggles if and only if CNTEN is assertedand all of the lower-order counter bits are 1. Like the binary ripple counter, asynchronousDOn-bit binary counterNOTcan be built with a fixed amountCOPYof logic perbit—in this case, a T flip-flop with enable and a 2-input AND gate.The counter structure in Figure 8-28 is sometimes called a synchronous synchronous serialserial counter because the combinational enable signals propagate serially from counterthe least significant to the most significant bits. If the clock period is too short,thereDOmay not be enough timeNOTfor a change in the counter’s LSBCOPYto propagate tothe MSB. This problem is eliminated in Figure 8-29 by driving each EN inputwith a dedicated AND gate, just a single level of logic. Called a synchronous synchronous parallelparallel counter, this is the fastest binary counter structure.counterDO NOT COPYCNTENEN Q Q0 Figure 8-29CLKA synchronous 4-bitTbinary counter withparallel enable logicDO NOTEN Q Q1COPYTEN Q Q2DO NOT COPYTEN Q Q3TCopyright © 1999 by John F. WakerlyCopying Prohibited
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Section *8.6 Iterative versus Seque
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References 687DOAs we mentioned in
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Exercises 689DO NOT COPY74x1692CLOC
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Exercises 691DO NOT COPYZ is assert
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Exercises 6938.54DOModify the ABEL
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Exercises 695DO NOT COPYSYNCINASYNC
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