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608 Chapter 8 Sequential Logic Design PracticesDO NOT COPYTable 8-12 ABEL program for a 74x163-like 4-bit binary counter.module Z74X163title '4-bit Binary Counter'DO" InputNOTpinsCOPYCLK, !LD, !CLR, ENP, ENT pin;A, B, C, D pin;" Output pinsQA, QB, QC, QDpin istype 'reg';DO NOT COPYRCOpin istype 'com';" Set definitionsINPUT = [D, C, B, A];COUNT = [QD, QC, QB, QA];DO NOT COPYequationsCOUNT.CLK = CLK;COUNT := !CLR & ( LD & INPUTDO NOT# !LD & (ENT & ENP)COPY& (COUNT + 1)# !LD & !(ENT & ENP) & COUNT);RCO = (COUNT == [1,1,1,1]) & ENT;DOendNOTZ74X163COPYTable 8-13 MInimized equations for the 4-bit binary counter in Table 8-12.QA := (CLR & LD & ENT & ENP & !QAQD := (CLR & LD & ENT & ENP & !QD & QC & QB & QADO NOT COPY# CLR & LD & !ENP & QA# CLR & !LD & D# CLR & LD & !ENT & QA# CLR & LD & QD & !QB# CLR & !LD & A);# CLR & LD & QD & !QC# CLR & LD & !ENP & QDQB := (CLR & LD & ENT & ENP & !QB & QA# CLR & LD & !ENT & QDDO# CLR & LD & QB & !QANOT# CLRCOPY& LD & QD & !QA);# CLR & LD & !ENP & QB# CLR & LD & !ENT & QBRCO = (ENT & QD & QC & QB & QA);# CLR & !LD & B);QC := (CLR & LD & ENT & ENP & !QC & QB & QADO# CLR & LD & QC & !QANOT COPY# CLR & LD & QC & !QB# CLR & LD & !ENP & QC# CLR & LD & !ENT & QC# CLR & !LD & C);Copyright © 1999 by John F. WakerlyCopying Prohibited
Section 8.4 Counters 609DOTable 8-13 shows the minimizedNOTlogic equations that ABELCOPYgenerates forthe 4-bit counter. Notice that each more significant output bit requires one moreproduct term. As a result, the size of counters that can be realized in a 16V8 oreven a 20V8 is generally limited to five or six bits. Other devices, including theX-seriesDOPLDs and some CPLDs,NOTcontain an XOR structureCOPYthat can realizelarger counters without increasing product-term requirements.Designing a specialized counting sequence in ABEL is much simpler thanadapting a standard binary counter. For example, the ABEL program inTable 8-12 can be adapted to count in excess-3 sequence (Figure 8-38 onpageDO603) by changing the equationsNOTas follows:COPYCOUNT := !CLR & ( LD & INPUT# !LD & (ENT & ENP) &((COUNT==12) & 3) # ((COUNT!=12) & (COUNT + 1))# !LD & !(ENT & ENP) & COUNT);DO NOT COPYRCO = (COUNT == 12) & ENT;PLDs can be cascaded to obtain wider counters, by providing each counterstage with a carry output that indicates when it is about to roll over. There aretwoDObasic approaches to generatingNOTthe carry output:COPY• Combinational. The carry equation indicates that the counter is enabled combinational carryand is currently in its last state before rollover. For a 5-bit binary up outputcounter, we haveDOCOUT = CNTEN &NOTQ4 & Q3 & Q2 & Q1 & Q0;COPYSince CNTEN is included, this approach allows carries to be rippled throughcascaded counters by connecting each COUT to the next CNTEN.• Registered. The carry equation indicates that the counter is about to enter registered carry outputDOits last state before rollover.NOTThus, at the next clock tick,COPYthe counter entersthis last state and the carry output is asserted. For a 5-bit binary up counterwith load and clear inputs, we haveCOUT := !CLR & !LD & CNTEN& Q4 & Q3 & Q2 & Q1 & !Q0DO# !CLR *NOT!LD * !CNTENCOPY& Q4 & Q3 & Q2 & Q1 & Q0# !CLR & LD& D4 & D3 & D2 & D1 & D0;The second approach has the advantage of producing COUT with less delay thantheDOcombinational approach.NOTHowever, external gates are nowCOPYrequired betweenstages, since the CNTEN signal for each stage should be the logical AND of themaster count-enable signal and the COUT outputs of all lower-order counters.These external gates can be avoided if the higher-order counters have multipleenable inputs.Copyright © 1999 by John F. WakerlyCopying Prohibited
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References 687DOAs we mentioned in
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Exercises 689DO NOT COPY74x1692CLOC
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Exercises 6938.54DOModify the ABEL
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Exercises 695DO NOT COPYSYNCINASYNC
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