chapter 8.pdf

Section 8.4 Counters 603DO NOT COPYCLOCKQ0DOQ1NOT COPYQ2Q3DO NOT COPYCOUNT 3 4 5 6 7 8 9 10 11 12 3Figure 8-38 Timing waveforms for the ’163 used as an excess-3 decimal counter.excess-3 decimal code, shown in Table 2-9 on page 45. Figure 8-37 shows theconnectionsDOfor a ’163 to countNOTin the excess-3 sequence. A NANDCOPYgate detectsstate 1100 and forces 0011 to be loaded as the next state. Figure 8-38 shows theresulting timing waveforms. Notice that the Q3 output has a 50% duty cycle,which may be desirable for some applications.A binary counter with a modulus greater than 16 can be built by cascading74x163s.DOFigure 8-39 showsNOTthe general connections for suchCOPYa counter. TheCLK, CLR_L, and LD_L inputs of all the ’163s are connected in parallel, so thatall of them count or are cleared or loaded at the same time. A master countenable(CNTEN) signal is connected to the low-order ’163. The RCO4 output isasserted if and only if the low-order ’163 is in state 15 andDO NOTCNTEN is asserted;COPYRCO4 is connected to the enable inputs of the high-order ’163. Thus, both thecarry information and the master count-enable ripple from the output of oneFigure 8-39 General cascading connections for 74x163-based counters.DO NOT COPY74x16374x16322CLOCKCLKCLK11RESET_LCLRCLRDO9NOT COPY9LOAD_LLDLD77CNTENENPENP1010ENTENT314314D0A QAQ0 D4A QAQ4413413D1B QBQ1 D5B QBQ5DO5NOT12COPY512D2C QCQ2 D6C QCQ6611611D3D QD Q3 D7D QDQ715RCO415RCORCORCO8U1U2Copyright © 1999 by John F. WakerlyCopying Prohibited