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Section 8.3 Sequential PLDs 591DOThe 22V10, whose basicNOTstructure is shown in Figure 8-22,COPYalso comes in a 22V1024-pin package, but is somewhat more flexible than the 20V8. The 22V10 doesnot have “architecture control” bits like the 16V8’s and 20V8’s, but it can realizeany function that is realizable with a 20V8, and more. It has more product terms,twoDOmore general-purposeNOTinputs, and better output-enableCOPYcontrol than the20V8. Key differences are summarized below:• Each output logic macrocell is configurable to have a register or not, as inthe 20V8R architecture. However, the macrocells are different from the16V8’s and 20V8’s, as shown in Figure 8-23.DO NOT COPY• A single product term controls the output buffer, regardless of whether theregistered or the combinational configuration is selected for a macrocell.• Every output has at least eight product terms available, regardless ofwhether the registered or the combinational configuration is selected. EvenDOmore product terms areNOTavailable on the inner pins, withCOPY16 available oneach of the two innermost pins. (“Innermost” is with respect to the righthandside of the Figure 8-22, which also matches the arrangement of thesepins on a 24-pin dual-inline package.)• The clock signal on pin 1 is also available as a combinational input to anyDO NOT COPYproduct term.• A single product term is available to generate a global, asynchronous resetsignal that resets all internal flip-flops to 0.• A single product term is available to generate a global, synchronous presetDOsignal that sets all internalNOTflip-flops to 1 on the rising edgeCOPYof the clock.• Like the 16V8 and 20V8, the 22V10 has programmable output polarity.However, in the registered configuration, the polarity change is made at theoutput, rather than the input, of the D flip-flop. This affects the details ofprogramming when the polarity is changed but does not affect the overallDO NOT COPYcapability of the 22V10 (i.e., whether a given function can be realized). Infact, the difference in polarity-change location is transparent when you usea PLD programming language such as ABEL.FigureDO8-23 Output logicNOTmacrocells for the 22V10: (a) registered;COPY(b) combinational.(a) CLKRegistered(b) CLKCombinationalSP AR output logic macrocellSP AR output logic macrocellDO NOT COPY8–16D Q8–16QCopyright © 1999 by John F. WakerlyCopying Prohibited

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