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578 Chapter 8 Sequential Logic Design PracticesDO NOT COPYWHY A LATCH? The microprocessor bus protocol in Figure 8-14 raises several questions:• Why not keep the address valid on ABUS for the entire operation? In a realsystem using this protocol, the functions of ABUS and DBUS are combinedDO NOT(multiplexed) onto one three-state busCOPYto save pins and wires.• Why not use AVALID as the clock input to a positive-edge-triggered register tocapture the address? There isn’t enough setup time; in a real system, the addressmay first be valid at or slightly after the rising edge of AVALID.• OK, so why not use AVALID to clock a negative-edge-triggered register? ThisDO NOTworks, but the latched outputs are availableCOPYsooner; valid values on ABUS flowthrough a latch immediately, without waiting for the falling clock edge. Thisrelaxes the access-time requirements of memories and other devices driven bythe latched outputs.DO NOT COPYUsing a PLD, the latching and decoding functions for the high-order bitscan be combined into a single device, yielding the block diagram in Figure 8-16.Compared with Figure 8-15, the “latching decoder” saves devices and pins, andmay produce a valid chip-select output more quickly (see Exercise 8.1).DO NOTTable 8-2 is an ABEL programCOPYfor the latching decoder. Since it operateson only the high-order bits ABUS[31..20], it can decode addresses only in1-Mbyte or larger chunks (2 20 = 1M). A read-only memory (ROM) is locatedin the highest 1-Mbyte chunk, addresses 0xfff00000–0xffffffff, and isselected by ROMCS. Three 16-Mbyte banks of read/write memory (RAM) areDO NOT COPYlocated at lower addresses, starting at addresses 0x00000000, 0x00100000, and0x00200000, respectively. Notice how don’t-cares are used in the definitions ofthe RAM bank address ranges to decode a chunk larger than 1 Mbyte. Otherapproaches to these definitions are also possible (e.g., see Exercise 8.2).DO NOTThe equations in Table 8-2 forCOPYthe chip-select outputs follow the D-latchtemplate that we gave on page 576. The expressions that select a device, such as“ABUS==ROM,” each generate a single product term, and each equation generatesthree product terms. Notice the use of the “retain” property in the pin declarationsto prevent the compiler from optimizing away the consensus terms.DO NOT COPYFigure 8-16latchingto individualUsing a combined ABUS[31:20]decoderdeviceaddress latching andchip-selectdecoding circuit.GinputsDO NOT20-bit latchCOPYABUS[19:0] D[19:0]to deviceQ[19:0]addressAVALID GinputsCopyright © 1999 by John F. WakerlyCopying Prohibited
Section 8.2 Latches and Flip-Flops 579DO NOT COPYmodule latchdecTable 8-2title 'Latching Microprocessor Address Decoder'ABEL programfor a latching" Inputsaddress decoder.AVALID, ABUS31..ABUS20pin;" LatchedDOand decoded outputsNOT COPYROMCS, RAMCS0, RAMCS1, RAMCS2 pin istype 'com,retain';ABUS = [ABUS31..ABUS20];ROM = ^hFFF;RAMBANK0DO= [0,0,0,0,0,0,0,0,.X.,.X.,.X.,.X.];NOT COPYRAMBANK1 = [0,0,0,0,0,0,0,1,.X.,.X.,.X.,.X.];RAMBANK2 = [0,0,0,0,0,0,1,0,.X.,.X.,.X.,.X.];equationsROMCSDO= AVALID & (ABUS==ROM)NOT# !AVALID & ROMCSCOPY# (ABUS==ROM) & ROMCS;RAMCS0 = AVALID & (ABUS==RAMBANK0) # !AVALID & RAMCS0# (ABUS==RAMBANK0) & RAMCS0;RAMCS1 = AVALID & (ABUS==RAMBANK1) # !AVALID & RAMCS1# (ABUS==RAMBANK1) & RAMCS1;RAMCS2DO= AVALID & (ABUS==RAMBANK2)NOT# !AVALID & RAMCS2COPY# (ABUS==RAMBANK2) & RAMCS2;end latchdecDO NOT COPYAfter seeing how easy it is to build S-R and D latches using combinationalPLDs, you might be tempted to go further and try to build an edge-triggered Dflip-flop. Although this is possible, it is expensive because an edge-triggeredflip-flop has four internal states and thus two feedback loops, consuming twoPLDDOoutputs. Furthermore, theNOTsetup and hold times and propagationCOPYdelays ofsuch a flip-flop would be quite poor compared to those of a discrete flip-flop inthe same technology. Finally, as we discussed in Section 7.10.6, the flow tablesof all edge-triggered flip-flops contain essential hazards, which can be maskedonly by controlling path delays, difficult in a PLD-based design.DO NOT COPY8.2.7 Registers and Latches in VHDLRegister and latch circuits can be specified using structural VHDL. For example,Table 8-3 is a structural VHDL program corresponding to the D latch circuit ofFigure 7-12 on page 443. However, writing structural programs is not really ourmotivationDOfor using VHDL;NOTour goal is to use behavioral programsCOPYto model theoperation of circuits more intuitively.Table 8-4 is a process-based behavioral architecture for the D latch thatrequires, in effect, just one line of code to describe the latch’s behavior. Note thatthe VHDL compiler “infers” a latch from this description—since the codeCopyright © 1999 by John F. WakerlyCopying Prohibited
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Section *8.6 Iterative versus Seque
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Section *8.6 Iterative versus Seque
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References 687DOAs we mentioned in
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Exercises 689DO NOT COPY74x1692CLOC
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Exercises 691DO NOT COPYZ is assert
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Exercises 6938.54DOModify the ABEL
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Exercises 695DO NOT COPYSYNCINASYNC
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