chapter 8.pdf

562 Chapter 8 Sequential Logic Design PracticesDO8.1NOTSequential Circuit DocumentationCOPYStandards8.1.1 General RequirementsBasic documentation standards in areas like signal naming, logic symbols, andschematic layout, which we introduced in Chapter 5, apply to digital systems asDOa wholeNOTand therefore to sequentialCOPYcircuits in particular. However, there areseveral ideas to highlight for system elements that are specifically “sequential”:• State-machine layout. Within a logic diagram, a collection of flip-flops andcombinational logic that forms a state machine should be drawn togetherDO NOTin a logical format on the sameCOPYpage, so the fact that it is a state machine isobvious. (You shouldn’t have to flip pages to find the feedback path!)• Cascaded elements. In a similar way, registers, counters, and shift registersthat use multiple ICs should have the ICs grouped together in the schematicso that the cascading structure is obvious.DO NOT COPY• Flip-flops. The symbols for individual sequential-circuit elements,especially flip-flops, should rigorously follow the appropriate drawingstandards, so that the type, function, and clocking behavior of the elementsare clear.DO•NOTState-machine descriptions. StateCOPYmachines should be described by statetables, state diagrams, transition lists, or text files in a state-machinedescription language such as ABEL or VHDL.• Timing diagrams. The documentation package for sequential circuitsDO NOTshould include timing diagramsCOPYthat show the general timing assumptionsand timing behavior of the circuit.• Timing specifications. A sequential circuit should be accompanied by aspecification of the timing requirements for proper internal operation (e.g.,maximum clock frequency), as well as the requirements for any externallyDO NOTsupplied inputs (e.g., setup- andCOPYhold-time requirements with respect to thesystem clock, minimum pulse widths, etc.).8.1.2 Logic SymbolsWe introduced traditional symbols for flip-flops in Section 7.2. Flip-flops areDOalwaysNOTdrawn as rectangular-shapedCOPYsymbols, and follow the same generalguidelines as other rectangular-shaped symbols—inputs on the left, outputs onthe right, bubbles for active levels, and so on. In addition, some specific guidelinesapply to flip-flop symbols:DO•NOTA dynamic indicator is placed onCOPYedge-triggered clock inputs.• A postponed-output indicator is placed on master/slave outputs that changeat the end interval during which the clock is asserted.• Asynchronous preset and clear inputs may be shown at the top and bottomof a flip-flop symbol—preset at the top and clear at the bottom.Copyright © 1999 by John F. WakerlyCopying Prohibited