chapter 8.pdf

Section 8.2 Latches and Flip-Flops 575common,DOactive-lowNOT COPYOE_L (output enable) input. As in the other registers thatwe’ve studied, the control inputs (CLK and OE_L) are buffered so that theypresent only one unit load to a device that drives them.One variation of the 74x374 is the 74x373, whose symbol is shown inFigureDO8-11. The ’373 uses DNOTlatches instead of edge-triggeredCOPYflip-flops. Therefore,its outputs follow the corresponding inputs whenever C is asserted, andlatch the last input values when C is negated. Another variation is the 74x273,shown in Figure 8-12. This octal register has non-three-state outputs and noOE_L input; instead it uses pin 1 for an asynchronous clear input CLR_L.DOThe 74x377, whose symbolNOTis shown in Figure 8-13(a),COPYis an edgetriggeredregister like the ’374, but it does not have three-state outputs. Instead,pin 1 is used as an active-low clock enable input EN_L. If EN_L is asserted(LOW) at the rising edge of the clock, then the flip-flops are loaded from the datainputs; otherwise, they retain their present values, as shown logically in (b).DO NOT COPY74x37374x273Figure 8-11Figure 8-121111CLogic symbol for theCLogic symbol for the11OE74x373 8-bit latch.CLR74x273 8-bit register.3232DO1D 1QNOT COPY1D 1Q42D 2Q 542D 2Q 573D 3Q 6 73D 3Q 689894D 4Q4D 4Q135D 5Q 12135D 5Q 12141514156D 6Q6D 6QDO NOT COPY17 1617 167D 7Q7D 7Q18 1918 198D 8Q8D 8QFigure 8-13 The 74x377 8-bit register with gated clock:DO(a) logic symbol;NOT(b) logical behavior of one bit.COPY(a)(b)74x37711CLK1DOENNOT COPY(19)32D Q 8Q1D 1Q4(18)CK2D 2Q 58D73D 3Q 6894D 4Q13DO5D 5Q 12NOT COPY(1)1415 EN_L6D 6Q17 167D 7Q18 19(11)8D 8QCLKCopyright © 1999 by John F. WakerlyCopying Prohibited