chapter 8.pdf

564 Chapter 8 Sequential Logic Design PracticesDO NOTThe solution to this problem isCOPYsimilar to the one adopted by programmerswho write self-documenting code using a high-level language. The key is toselect a representation that is both expressive of the designer’s intentions andthat can be translated into a physical realization using an error-free, automatedDOprocess.NOT(You don’t hear many programmersCOPYscreaming “Compiler bug!” whentheir programs don’t work the first time.)The best solution (for now, at least) is to write state-machine “programs”directly in a high-level state-machine description language like ABEL orVHDL, and to avoid alternate representations, other than general, summaryDOwordNOTdescriptions. Languages like ABELCOPYand VHDL are easily readable andallow automatic conversion of the description into a PLD-, FPGA-, or ASICbasedrealization. Some CAD tools allow state machines to be specified andsynthesized using state diagrams, or even using sample timing diagrams, butthese can often lead to ambiguities and unanticipated results. Thus, we’ll useDOABEL/VHDLNOTapproach exclusively forCOPYthe rest of this book.8.1.4 Timing Diagrams and SpecificationsWe showed many examples of timing diagrams in Chapters 5 and 7. In thedesign of synchronous systems, most timing diagrams show the relationshipDObetweenNOTthe clock and various input,COPYoutput, and internal signals.Figure 8-1 shows a fairly typical timing diagram that specifies the requirementsand characteristics of input and output signals in a synchronous circuit.The first line shows the system clock and its nominal timing parameters. Theremaining lines show a range of delays for other signals.DO NOT COPYFor example, the second line shows that flip-flops change their outputs atsome time between the rising edge of CLOCK and time t ffpd afterward. Externalcircuits that sample these signals should not do so while they are changing. Thetiming diagram is drawn as if the minimum value of tDO NOT COPYffpd is zero; a completeFigure 8-1CLOCKA detailed timingtDO NOTH tdiagram showingpropagation delaysCOPYLt clkflip-flopand setup and holdoutputstimes with respect tot ffpdthe clock.combinationaloutputsDO NOTt combCOPYflip-flopinputst setupsetup-time marginCopyright © 1999 by John F. Wakerlyt holdCopying Prohibited