chapter 8.pdf

Section 8.4 Counters 601DO NOT COPYCLOCKQADOQBNOT COPYQCQDDO NOT COPYRCOCOUNT 0 1 2 3 4 5 6 7 8 9 0Figure 8-34 Clock and output waveforms for a free-running divide-by-10 counter.DO NOT COPYas provided by the 74x161. The ’161 has the same pinout as the ’163, but its 74x161CLR_L input is connected to the asynchronous clear inputs of its flip-flops.The 74x160 and 74x162 are more variations with the same pinouts and 74x160general functions as the ’161 and ’163, except that the counting sequence is 74x162modifiedDOto go to state 0 afterNOTstate 9. In other words, theseCOPYare modulo-10counters, sometimes called decade counters. Figure 8-34 shows the output decade counterwaveforms for a free-running ’160 or ’162. Notice that although the QD and QCoutputs have one-tenth of the CLK frequency, they do not have a 50% duty cycle,and the QC output, with one-fifth of the input frequency, does not have aconstantDOduty cycle. We’ll showNOTthe design of a divide-by-10 counterCOPYwith a 50%duty-cycle output later in this subsection.Although the ’163 is a modulo-16 counter, it can be made to count in amodulus less than 16 by using the CLR_L or LD_L input to shorten the normalcounting sequence. For example, Figure 8-35 shows one way of using the ’163as aDOmodulo-11 counter. TheNOTRCO output, which detects state 15,COPYis used to force74x163Figure 8-352CLOCKCLKUsing the 74x163 asRPU 1CLRa modulo-11 counterDO NOT COPY9LDwith the counting7ENPsequence 5, 6, …, 15,10ENT5, 6, ….314+5 VA QAQ0413B QBQ1DO NOT512COPYC QCQ2611RD QD Q315 74x04RCOCNT15 1 2U1CNT15_L U2Copyright © 1999 by John F. WakerlyCopying Prohibited