Medical Applications Guide (Rev. B - Mouser Electronics

52➔Medical ImagingUltrasound/Portable UltrasoundTMS320C645x DSP Generation, Fixed PointHighest-Performance DSPsTMS320C6455Get samples, datasheets, tool and app reports at:www.ti.com/sc/device/TMS320C6455The TMS320C64x+ DSPs (including the TMS320C6455 IC) arethe highest performance, fixed-point DSP generation in theTMS320C6000 DSP platform. The C6455 IC is based on thethird-generation, high-performance, advanced VelociTI very-longinstruction-word (VLIW) architecture developed by TI, which allowsthese DSPs to be used for applications including video and telecominfrastructure, imaging/medical and wireless infrastructure (WI).The C64x+ ICs are upward code-compatible from previous ICsthat are part of the C6000 DSP platform.Key Features• Based on the new TMS320C64x+ core 720MHz, 850MHz, 1GHz• Memory:• 32KB L1D, 32KB L1P Cache/SRAM• 2MB L2, 256K Cache/SRAM, remainder SRAM only• Acceleration• Viterbi decoder co-processor (VCP)• Turbo decoder co-processor (TCP)Applications• Serial RapidIO: 10Gb/s full duplex• Other high-bandwidth peripherals: Gigabit Ethernet MAC, UTOPIA,PCI-66, HPI• Two EMIFs: 32-bit DDR2, 64-bit EMIFL1P Cache/SRAM32KBytes256DSP Core8*32L1D Cache/SRAM32KBytes1281281284 32xPLLVCPTCPGPIO 162MB L2(Up to 256KB Cache)EDMA 3.0Switched Central Resource4x SerialRapidIOEMIF 64DDR2McBSP 0/1PCI 66andGEMACorHPIandGEMACorUTOPIATimer 0/1I2CTMS320C67x DSP Generation, Floating PointHigh-Performance DSPsTMS320C6727Get samples, datasheets, tool and app reports at: www.ti.com/c6000The TMS320C672x is the next generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672xincludes the TMS320C6727, TMS320C6726, and TMS320C6722 ICs.Enhanced C67x+ CPU — The C67x+ CPU is an enhanced versionof the C67x CPU used on the C671x DSPs. It is compatible with theC67x CPU but offers significant improvements in speed, code density,and floating-point performance per clock cycle. At 300MHz, the CPU iscapable of a maximum performance of 2400MIPS/1800 MFLOPS byexecuting up to eight instructions (six of which are floating-pointinstructions) in parallel each cycle. The CPU natively supports 32-bitfixed-point, 32-bit single-precision floating-point, and 64-bit doubleprecisionfloating-point arithmetic.Efficient Memory System — The memory controller maps the largeon-chip 256K-byte RAM and 384K-byte ROM as unified program/datamemory. Development is simplified since there is no fixed divisionbetween program and data memory size as on some other ICs. Thememory controller supports single-cycle data accesses from theC67x+ CPU to the RAM and ROM.Key Features• 100% code-compatible DSPs• Advanced VLIW architecture• Up to eight 32-bit instructions executed each cycle• Eight independent, multi-purpose functional units and up tosixty-four 32-bit registers• Advanced DSP C compiler and assembly optimizer maximizeefficiency and performanceApplications• Medical and digital imaging• 3D graphicsControlRegistersControlLogicProgram/Data RAM256KBytesC67x+ CPU CoreTestIn-CircuitEmulationInterruptsInstruction DecodeInstruction DispatchProgram FetchData Patch A Data Patch BInstruction Cache32KBytesA Register File B Register FileD2 M2 S2 L2L1 S1 M1 D1BIOS/DSPLIB/FastRTSin ROM384 KBytesMemoryControllerHigh-PerformanceCrossbar SwitchJTAGEmulationControlMcASP DMA BusPeripheral Configuration BusMcASP0McASP1McASP2SPI1SPIOIIC0IIC1RTI TimerUniversal Host PortInterfacePLL Clock GeneratorTMS320C6455/TMS320C6454 DSP block diagram.dMAXExternal MemoryInterfaceTMS320C6727 DSP block diagram.Medical Applications Guide Texas Instruments 2Q 2007