DESIGN AND DEVELOPMENT OF MEDICAL ELECTRONIC ...

198 ELECTROMAGNETIC COMPATIBILITY AND MEDICAL DEVICESby logic signals during that clock period: path delays, setup and latchup times, logic gatepropagation delays, and skew. As clock frequencies increase, the time left over for logicalcomputation decreases, up to the point that skew often causes system failures due toincomplete processing during a clock cycle.For this reason, PCB tracks that distribute the clock must be tuned so that the delayfrom the clock driver to each load is the same. Whenever possible, the loading on eachtrack carrying the clock should be the same, and in this case skew is minimized by makingall tracks the same length. For unbalanced loads, delay times can be tuned through RCterminations or by careful adjustment of the track lengths.Crosstalk and Vulnerable PathsCrosstalk is the noise induced into a track by the presence of a pulse stream in an adjacenttrack. In essence, crosstalk is EMI caused by the product on itself. The amount of crosstalkis affected by track spacing, routing, signal direction, and grounding. The major problemwith crosstalk arises when the voltages induced on a quiet line are sufficient to be detectedas a change in logic state by the receivers of that line. In high-speed systems, the capacitiveand inductive coupling between lines is considerable, and crosstalk must be reducedthrough appropriate design.First, proper transmission line termination reduces the amount of radiated energy from adriven track, and spurious emissions that nevertheless escape can be shielded through theuse of grounded guards. This design consideration is particularly important for lines drivenwith high-voltage, high-current, and high-frequency signals. Floating lines connected to highimpedancereceivers are notably sensitive to crosstalk, and proper shielding, as well as maintainingthem at a distance from possible radiating tracks, must be ensured. In addition, it ispossible to see from transmission line theory that crosstalk between two adjacent tracks isminimized if the two signals flow in the same direction.The analysis should be extended to identifying potential coupling paths between signallines and RFI sources (including ESD) and then taking steps to minimize them throughproper placement of PCB tracks and components. For example, shields can be reinforcedwhere transformers and heat sinks are placed, the areas of loops formed by PCB tracksshould be minimized, and magnetic coupling paths should be oriented orthogonally.Finally, remember that components, connectors, and mounting parts that can beaccessed from the outer world are very often the paths of entry into a device’s circuit forEMI and especially for ESD. Even an exposed metallic screw on an otherwise insulatingpanel can make it possible for unwanted signals to get into the circuit and cause interference.Common panel-mounted vulnerable parts include membrane keyboards, LEDs, potentiometers,connectors, and switches, together with their mounting hardware.Analysis of Circuit Board PerformanceAlthough you may consider such tools as a time-domain reflectometer or an RF network analyzeras belonging strictly to a communications lab, these can aid considerably in the designof circuit boards for high-speed and high-immunity applications. These tools are capable ofmeasuring the actual impedances, time delays, and complex reflection coefficients of a circuit.These measurements often show that calculations of these parameters result in verycrude estimates that have to be improved on for good circuit performance. In most cases, theiterative process of design will require building and evaluating a test board to determine ifthe original design considerations were effective. This test board is usually not populatedwith the actual active components, but the PCB tracks, passive components, sockets, andconnectors, as well as the terminated dummy IC packages, form a network of transmissionlines that can be analyzed with confidence.