PIC18F to PIC24F Migration: An Overview - Microchip

These errors always force an immediate jump tospecific interrupt vectors. The two most serious errors(Address Decode and Oscillator Failure) are hardtraps; these must be cleared before the CPU executioncan continue. All traps have their own individual flag bit.In addition to these unmaskable events, the PIC24Farchitecture can be expanded at a future time toinclude up to four additional traps.PIC18F architecture does not have an equivalent to thehardware trap. PIC18F stack error events are treatedas Resets.BIT NAME CHANGES AND MAPPINGPIC24F devices maintain the same general nomenclaturefor interrupt bit names as PIC18F devices, with twoimportant differences. Both families maintain interruptenable, flag and priority bits that are generically namedxxxIE, xxxIF and xxxIP (where ’xxx’ is the mnemonic forthe interrupt source).The first major difference is the presence of three interruptpriority bits for each source, instead of the oneused for PIC18F devices. These bits, genericallynamed xxxIP2 through xxxIP0, allow the interrupt to beassigned one of eight relative priority levels.The other difference is the number of interrupt sources.While many interrupts have the same (or very similar)name as PIC18F devices, others are new. Other interruptshave similar names but have a different meaningfrom their PIC18F counterparts. Users should refer tothe appropriate PIC24F device data sheet for acomplete list of interrupts and their meanings.SETUP AND ENABLING INTERRUPTSTo set up and enable interrupts on PIC18F devices:Required Steps:1. Clear the interrupt flag status bit associated withthe peripheral in the associated PIRx orINTCONx register.2. Enable the interrupt source by setting the interruptenable control bit associated with the sourcein the appropriate PIEx or INTCONx register.Note: The interrupt flag still needs to be clearedprior to exiting an ISR.Optional Step:Select the user-assigned priority level for the interruptsource by writing to the control bits in the RCON register;select high priority or low priority using the priority bit inthe corresponding IPRx register. The interrupt priorityfeature is enabled by setting the IPEN bit (RCON).To set up and enable interrupts on PIC24F devices:Required Steps:1. Set the NSTDIS bit (INTCON1) if nestedinterrupts are not desired.2. Clear the interrupt flag status bit associated withthe peripheral in the associated IFSx register.3. Enable the interrupt source by setting the interruptenable control bit associated with thesource in the appropriate IECx register.Note:Optional Step:Select the user-assigned priority level for the interruptsource by writing the control bits in the appropriate IPCxregister. The priority level will depend on the specificapplication and type of interrupt source. If multiple prioritylevels are not desired, the IPCx register control bit forall enabled interrupt sources may be programmed to thesame non-zero value.Note:The Interrupt/trap flag still needs to becleared prior to exiting an ISR.Upon Reset, all interrupts are assigned adefault priority level of 4.DISABLING USER INTERRUPTSTo disable interrupts on PIC18F devices, it is onlynecessary to clear the GIE bit (GIEH or GIEL if prioritylevels are used).To disable user interrupts on PIC24F devices, thesesteps are required:1. Push the current STATUS register value ontothe software stack using the PUSH instruction.2. Force the CPU to priority level 7 by inclusiveORing the value OEh with the low byte of theSTATUS register (SRL). To enable user interrupts,the POP instruction may be used to restorethe previous STATUS register value.Note: The DISI instruction allows interrupts ofpriority levels 1-6 to be disabled for a fixedperiod of time.MIGRATION CONSIDERATIONSPIC18F architecture only has the ability to assign eitherhigh or low priority interrupts to individual sources.PIC24F architecture allows the assignment of multiplepriority levels for interrupts (priorities 0 through 7 areuser defined and priorities 8 through 15 are hardwaredefined). At the very least, interrupts in native PIC18Fapplications will need to be re-assessed, and theirpriority levels redefined in PIC24F terms.For both PIC18F and PIC24F devices, the RETFIEinstruction exits an Interrupt Service Routine (ISR), butthis instruction does behave slightly different dependingon the microcontroller. For PIC18F, this instructionwill set the GIE bit to re-enable global interrupts. Sincethe GIE bit does not exist for PIC24F, this instructionwill restore the previous priority level.DS39764A-page 18© 2006 Microchip Technology Inc.