PIC18F to PIC24F Migration: An Overview - Microchip

Serial Peripheral Interface (SPI)The PIC24F SPI peripheral is a superset of the PIC18Farchitecture and many of the features use the samepin, register and bit names. Most of the 64-pin andlarger PIC24F pin count devices have two SPI peripherals,as do the larger PIC18F pin count devices. ThePIC24F SPI peripheral is considered a “stand-alone”peripheral, where PIC18F devices incorporate the SPIfunction into the larger Master Synchronous Serial Port(MSSP) peripheral, which also includes I 2 C.The functionality of a synchronous USART is supportedin the PIC24F SPI, leaving the asynchronous,LIN and IrDA ® functions for the PIC24F UART. See the“Universal Asynchronous Receiver/Transmitter(UART)” section on page 38 for additional PIC18FEUSART and PIC24F UART differences.Both SPI peripherals support Master and Slave mode,selectable active clock edge and clock Idle state. Mastermode can select when data is sampled at a varietyof clock rates. The slave select feature is also commonbetween the two architectures.A comparison of SPI module features is provided inTable 23.BIT NAME CHANGES AND MAPPINGMany of the PIC24F bit and register names will lookfamiliar to a PIC18F user, as shown in Table 24.TABLE 23: COMPARISON BETWEEN PIC18F AND PIC24F SPI FEATURESFeature Description PIC18F PIC24FSelectable Clock Polarity Yes YesSelectable Clock Edge Yes Yes2-Wire Support Yes YesSlave Select Option Yes YesFIFO Buffer No YesTransfer Data Width 8 8/16Frame Mode Support No YesSynchronous USART Functionality in SPI No YesTABLE 24:SPI BIT NAMING CONVENTION AND FUNCTIONALITYFunctionality PIC18F PIC24FClock Polarity CKE CKEClock Edge CKP CKPSPI Data Buffer SSPxBUF SPIxBUFTransfer or Reception States BF SPITBF and SPIRBFSPI Event Occurs SSPxIF Interrupt Flag SPIxIFOverflow Status bit SSPOV SPIROVSampling Time SMP SMPSPI Modes and FrequencySSPMMSTENPPRESPRESSENSDO Disable TRIS DISSDODS39764A-page 34© 2006 Microchip Technology Inc.