PIC18F to PIC24F Migration: An Overview - Microchip

NEW PIC24F A/D FEATURESMany of the improvements of the PIC24F A/D are likelyto add value to applications migrating from the PIC18Farchitecture.• Enhanced Sampling Speed and Throughput:The minimum A/D clock period has been reducedfrom 750 ns to 75 ns, providing conversion ratesup to 500 ksps (thousand samples per second).• Flexible Results Buffering: The results buffer canbe configured as two 8-word buffers or one16-word buffer. In Two 8-Word Buffer mode, resultscan be written either sequentially through eachbuffer or alternately between the two buffers.• Output Formats: Conversion data can be providedin one of four user-selectable data formats.• Input Scanning: Multiple analog channels can besuccessively scanned across two sets ofmultiplexed inputs using the Automatic ChannelScan mode option.• Individual Pin Configuration: Each of theanalog input pins can be individually selected forAnalog Input mode, instead of as part of asequence of pins.• Differential Conversion: This conversion modeallows the direct measurement of the voltagedifference between two analog inputs.UNSUPPORTED PIC18F FEATURESAll PIC18F A/D converter features are supported in thePIC24F A/D.MIGRATING A TYPICAL SETUPPreparing for a PIC24F A/D conversion is very similarto setting up a PIC18F conversion. One or more pinsare configured as an analog input and the A/D parametersselect the acquisition time and conversion clock.The A/D is enabled. If an interrupt is needed, the A/Dinterrupt flag is cleared and the interrupt is enabled.After the minimum required acquisition time hasexpired, either in software or automatically by themodule, the A/D conversion is started. When theinterrupt occurs or the DONE bit is read high, the resultis available in the designated result register.To prepare the PIC24F A/D for a comparable PIC18Fconversion, perform the following:1. Select which pins will become A/D inputs(AD1PCFG).2. Determine A/D voltage references(AD1CON2).3. Select A/D clock divider (AD1CON3) ordedicated RC (AD1CON3).4. Choose whether sampling will begin automaticallyafter the previous conversion or by software(AD1CON1).5. Select the trigger source to begin the conversion,either by software, an INT0 transition,Timer3 compare or automatically by the module(AD1CON1).6. Determine whether the results will be stored asinteger, signed integer, fractional or signedfractional format (AD1CON1).7. To match the PIC18F architecture, generate aninterrupt on every conversion by clearing theSMPI (AD1CON2) bits.8. Enable the module (AD1CON1).9. If desired, enable the A/D interrupt by clearingthe interrupt flag (IFS0), setting theinterrupt enable bit (IEC0) and setting theinterrupt priority to 7 (IPC3).MIGRATION CONSIDERATIONS• The analog input voltage range of the PIC24F issmaller than PIC18F devices due to the smallerVDD range of the PIC24F device family. The voltagerange of the PIC24F is 2.0V to 3.6V, whereasthe range for most PIC18F devices is 2.0V to 5.5V.Note:For both architectures, the analog voltagerange must not exceed 0.3V above VDD orbelow VSS.• The analog input impedance for the PIC24Fmodule is 2.5 kΩ. Many PIC18F devices are10 kΩ, although 2.5 kΩ is recommended.• For the PIC24F module, the module’s internalsampling capacitor is 4.4 pF, typical; for thePIC18F module, it is 25 pF, typical. The reducedcapacitance increases the affect of the externalcapacitance on the analog input.• When configuring the A/D to use the conversionclock, several factors will affect the PIC24F dividerselection. These include the reduced TAD and theinstruction rate. The PIC24F conversion clock isbased on the instruction clock, TCY/2, where thePIC18F is based on FOSC/2. Due to differentinstruction rates for a given system clock frequency,the smallest period for the PIC24F A/D clock divideris one FOSC period and two for PIC18F.DS39764A-page 42© 2006 Microchip Technology Inc.