PIC18F to PIC24F Migration: An Overview - Microchip

Memory Map and Program MemoryBoth PIC18F and PIC24F architectures use the samegeneral schema for their program memory spaces.Aside from the self-evident differences in width,PIC24F devices also incorporate a larger addressingrange and enhanced visibility features in data space.The organization of the space and the location ofnon-program memory features also differ somewhat,and must be considered when porting an application.The key differences between the memory organizationof PIC18F and PIC24F devices are presented inTable 6.TABLE 6:COMPARISON OF PIC18F AND PIC24F PROGRAM MEMORY ARCHITECTURESFeature PIC18F PIC24FOrganization 16-bit, byte addressable 24-bit, word addressableTotal Addressable Range 4 Mbytes (22-bit magnitude) 16 Mbytes (24-bit magnitude)Maximum Available User Program Space 2 Mbytes (FFFFFh) 8 Mbytes (7FFFFFh)(upper boundary address)Boot Block Support Most devices NoInterrupt/Reset/Trap Vectors 00h, 08h, 18h 00h to 1FFhConfiguration Word Locations 300000h to 30000Fh Last 2 implemented locations inprogram memoryDevice ID Locations 3FFFFE and 3FFFFFh FF0000h and FF0002hORGANIZATIONThe PIC18F program space is organized as 16-bitwords, but is addressable in terms of bytes. Thismeans that the upper or lower byte of any word can beindividually addressed by a pointer. To maintain wordalignment for code execution, the memory space isaligned on the Least Significant Byte (LSB) of eachword, and the program counter increments by 2 duringnormal execution.The PIC24F program space has a different, but parallelstructure. It is physically organized as 24 bits wide, butis addressed as 16-bit words. Thus, an instruction isconsidered to be two words, not 3 bytes. Each wordcan be individually addressed with even addressesrepresenting the lower word of an instruction and oddaddresses the upper word. To maintain instructionalignment, the memory space is aligned on evenwords; the program counter increments by 2 duringnormal execution.Since a PIC24F instruction is three bytes wide, theMost Significant Byte of an instruction finds itself alonein the most significant word of the instruction as it isstored in memory. To maintain word alignment whenreading from, or writing to program memory, a“phantom byte” of 00h is added before the MSB to giveit the proper word length (Figure 2). The value reflectsthat this byte is not actually implemented in physicalprogram memory.Even with its word-aligned addressing, any single bytewithin the program space can be individually read orwritten. The PIC24F TBLRD and TBLWT commands areextended to allow an individual upper or lower byte ofany word to be accessed. Keep in mind that the upperbyte of any upper word (odd address) will always be00h, and cannot be written to, for reasons previouslydiscussed.FIGURE 2:PIC24F PROGRAM MEMORY ORGANIZATIONMSWAddressMost Significant WordLeast Significant WordPC Address(LSW Address)000001h000003h000005h000007h00000000000000000000000000000000231680000000h000002h000004h000006hProgram Memory‘Phantom’ Byte(read as ‘0’)Instruction Width© 2006 Microchip Technology Inc. DS39764A-page 7