PIC18F to PIC24F Migration: An Overview - Microchip

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NEW PIC24F FEATURES• Open-drain inputs, when enabled, are active forboth port and peripheral activities. The I 2 C pinsalready have this function and are unaffected bythe ODCx register setting.• The Parallel Master Port (PMP) inputs are uniquefor the input buffer and can be software selectedas either a TTL or Schmitt Trigger (ST) inputbuffer. This feature is available through thePADCFGx register.• Digital-only pins are 5.5V input tolerant and areconvenient for interfacing into 5V components.• Additional pins are available forinterrupt-on-change and open-drainconfigurations.• The PMP is now a separate peripheral and notintegrated into the I/O port functions as was thePIC18F Parallel Slave Port (PSP). Please see theproduct data sheet for additional information.• Pull-ups are only available on PORTB in PIC18Fdevices and have a single enable bit to control allpull-ups. PIC24F supports pull-ups that can beselectively enabled on individual pins.• Interrupt-on-change on PIC18F devices is alsoimplemented with a single control bit for threePORTB pins. PIC24F interrupt-on-change pinscan all be individually enabled.UNSUPPORTED PIC18F FEATURESThe PIC24F port architecture does not permit the portoutput to drive the peripheral input. The user musteither configure the pin as a peripheral input, or portoutput, but not both.MIGRATION CONSIDERATIONS• Enabling a digital or analog input or output onto apin with a configurable open-drain option will notcause the pull-up to be automatically disabled.The pull-up is not disabled if the pin has a configurableopen-drain option. It is important to disablethe pull-up in software when it is not needed.• Pins without an analog function can tolerate inputvoltages up to 5.5V. This can minimize hardwarechanges when migrating from a PIC18F device. Ahigher voltage output can be created by adding anexternal pull-up resistor on the pin and writing azero to the data latch. Setting the TRIS bit will pullthe output up to the supply voltage and clearingthe TRIS bit will output a digital zero.• Drive strength, slew rate and input voltage thresholdscan change automatically when a peripheralis enabled. It is important to review the specificdata sheets for differences between devices.• Most of the input buffers for PIC24F devices areSchmitt Trigger (ST). Verify that the output levelsof associated components meet the ST inputvoltage thresholds.DS39764A-page 28© 2006 Microchip Technology Inc.
Timers (Timer1, Timer2/3 and Timer4/5)PIC24F timers support all of the PIC18F nanoWattfeatures, which include Asynchronous and SynchronousCounter modes, Timer modes and 32 kHz crystalsupport. PIC24F timers are designed to have moregeneric functions, whereas PIC18F timers are intendedfor dedicated purposes, such as PWM clock sources ora generic timer function. Each PIC24F 16-bit timer hasa dedicated period register, selectable prescaler andperiod match flag, and can operate in either Counter orTimer mode. PIC24F timers add new features, such asthe ability to combine two timers into a single 32-bittimer and a timer gate option.TABLE 19: COMPARISON BETWEEN PIC18F AND PIC24F TIMER FEATURESFeature Description PIC18F PIC24FTimer Width 8/16-bit 16/32-bitGeneral Purpose Timer Mode All timers All timersAsynchronous Counter Mode Timer1 and 3 Timer1, 2 and 4Synchronous Counter Mode Timer0, 1 and 3 All timersPeriod Register Timer2 and 4 All timers32 kHz Crystal Support Timer1 Timer1Timer Gate Option No All timersPrescaler All timers All timersPostscaler Timer2 and Timer4 NoSpecial Event Trigger Yes YesSystem Clock Source Rate FOSC/4 FOSC/2Although all timer functionality of the PIC18F nanoWattdevices is available in the PIC24F family, different functionsmay reside in different timers. Like the PIC18F, allPIC24F timers can operate using the system clock asthe clock source. Where Asynchronous Counter modewas available in only Timer1 and 3 for PIC18F, thisfunction is available in Timer1, 2 and 4 for PIC24F.Synchronous Counter mode is provided in all PIC24Ftimers, as well as providing a dedicated period register.The period register resets the timer on a clock cyclematch and sets the interrupt flag in both architectures.However, when using the PIC24F period register,ensure the timer gate option is disabled.Prescalers are available in both architectures. PIC18Ftimers have different prescale ranges, but PIC24Ftimers use a standard range for all timers (1:1, 1:8, 1:64and 1:256).Both architectures support 32 kHz crystals throughTimer1, which can be optionally used as an accurate,low-power system clock source. Refer to the “Oscillator”and “Power-Saving Features” sections on pages 19and 23, respectively, for more information on usingTimer1 as a system clock.Other device similarities include:• Timers can operate if the device is in Sleep modewhen the timer is configured for AsynchronousCounter mode or Timer1 32 kHz Crystal mode.• All timer modes are available in Idle mode sincethe peripheral has a clock source.• Both Sleep and Idle mode can be exited on atimer interrupt event.• A Special Event Trigger is available to start anA/D conversion. Refer to the product data sheetfor which timer(s) is capable of generating aSpecial Event Trigger.TABLE 20: PIC18F AND PIC24F BIT EQUIVALENT TIMER FUNCTIONSFunctionality PIC18F PIC24FTimer Enable TMRxON TONDouble Read/Write Buffer Mode RD16 T32Timer1 System Clock Status T1RUN COSC2:COSC0 = 100(OSCCON)Timer Prescale Select TxCKPSx TCKPSxTimer1 Oscillator Enable T1OSCEN SOSCEN (OSCCON)Timer External Clock Synchronization TxSYNC TSYNCTimer Clock Source Select TMRxCS TCSTimer Postscale Select TxOUTPSx N/A© 2006 Microchip Technology Inc. DS39764A-page 29
Page 1 and 2: PIC18F to PIC24F Migration: An Over
Page 3 and 4: W REGISTERSAll PIC18F devices have
Page 5 and 6: SUPPORTED DATA TYPESAside from bit-
Page 7 and 8: Memory Map and Program MemoryBoth P
Page 9 and 10: INTERRUPT/RESET/TRAP VECTORSIn PIC1
Page 11 and 12: Data Memory SpaceThe PIC24F data me
Page 13 and 14: Resets and Start-up TimingThe PIC24
Page 15 and 16: ADDITIONAL PIC24F RESETSBeyond the
Page 17 and 18: Interrupt ControllerThe PIC24F inte
Page 19 and 20: OscillatorThe PIC24F oscillator sys
Page 21 and 22: INTERNAL RC OSCILLATORS (INTOSC/FRC
Page 23 and 24: Power-Saving FeaturesPIC24F power-s
Page 25: Watchdog Timer (WDT)The Watchdog Ti
Page 30 and 31: NEW PIC24F FEATURESThe most apparen
Page 32 and 33: In Full-Bridge mode, the PIC18F PWM
Page 34 and 35: Serial Peripheral Interface (SPI)Th
Page 36 and 37: Inter-Intergrated Circuit (I 2 C)Th
Page 38 and 39: Universal AsynchronousReceiver/Tran
Page 40 and 41: TRANSMISSION SETUP (8-BIT DATA MODE
Page 42 and 43: NEW PIC24F A/D FEATURESMany of the
Page 44 and 45: NEW PIC24F COMPARATOR MODULEFEATURE
Page 46 and 47: NOTES:DS39764A-page 46© 2006 Micro
Page 48 and 49: TABLE A-1:PIC18FInstructionPIC18F A
Page 54: WORLDWIDE SALES AND SERVICEAMERICAS

PIC18F to PIC24F Migration: An Overview - Microchip

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