PIC18F to PIC24F Migration: An Overview - Microchip

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Universal AsynchronousReceiver/Transmitter (UART)The new PIC24F Universal Asynchronous ReceiverTransmitter (UART) module is a full-duplex, asynchronoussystem with enhanced functionality over the PIC18FEnhanced Universal Synchronous AsynchronousReceiver Transmitter (EUSART) module. Some of thenew PIC24F UART module features include increasedbaud rate, parity hardware support (even/odd/none) for8-bit data, selectable Idle polarity, software Stop in Idle,improved interrupt options and hardware flow controlsupports. Table 29 summarizes the comparison betweenthe PIC18F EUSART and PIC24F UART.Note:The PIC24F UART does not supportsynchronous communications. If synchronousserial communication is required, usethe SPI module instead.TABLE 29:COMPARISON BETWEEN PIC18F AND PIC24F UART FEATURESFeatures PIC18F EUSART PIC24F UARTAsynchronous (full-duplex) Operation with:- Auto-Wake-up on Character Reception- Auto-Baud Calibration- 12-Bit Break Character TransmissionFull-Duplex 8 or 9-Bit Data TransmissionYesYesthrough TX and RX pinsSupport for 9-Bit Mode with Address DetectYesYes(9th bit = 1)Hardware Flow Control Option with CTS andNoYesRTS pinsNumber of Stop bits 1 1 or 2Selectable Idle Polarity No YesBaud Rate Generator Dedicated 8-bit/16-bit 16-bitBRG Prescaler Yes YesBaud Rate rangeYes300 bps to 115 kbpsat 0.25-10 MIPSYes15 bps to 1 Mbpsat 16 MIPSIrDA ® Encoder and Decoder Logic No Yes16x Baud Clock Output for IrDA Support No YesFIFO Transmit Data Buffer No YesFIFO Receive Data Buffer No YesLoopback Mode for Diagnostic Support No YesHardware Parity Support (8-bit data)NoYes(can be implemented in software)Parity Error Detection No YesHardware Sync Byte Generation Yes YesSupport for Sync and Break Characters Yes YesWake-up Enable Yes YesFraming and Buffer Overrun Error Detection Yes YesSoftware Stop in Idle Option No YesInterrupt Options (see “Interrupt Controller”on page 17)Transmit and ReceiveTransmit, Receive and UARTError EventDS39764A-page 38© 2006 Microchip Technology Inc.
TABLE 30:UART BIT NAMING CONVENTION AND FUNCTIONALITYFunctionality PIC18F PIC24FAuto Baud Detect Enable bit/Auto-Baud Enable bit ABDEN ABAUDAddress Detect Enable bit/Address Character Detect bitADDENADDEN(bit 8 of received data = 1)High Baud Rate Select bit:BRGHBRGH(PIC18F high/low-speed, PIC24F 4x/16x baud clock)Continuous Receive Enable bit CREN (receiver only) UARTEN(transmitter and receiver)Framing Error bit/Framing Error Status bit (read-only) FERR FERROverrun Error bit/Receive Buffer Overrun Error Status bitOERROERR(clear/read-only)Receive Operation Idle Status bit/Receiver Idle bitRCIDLRIDLE(read-only)EUSART Receive Interrupt Flag bit (PIC18F)RCIFUxRXIFUART1 Receiver Interrupt Flag Status bit (PIC24F)Receive Buffer Data Available bit (read-only)URXDA9th bit of Received Data bit RX9D UxRXREG(word read needed)9-Bit Receive Enable bit/Parity and Data Selection bits RX9 PDSEL1:PDSEL09-Bit Transmit Enable bit/Parity and Data Selection bitsTX9Send Break Character bit SENDB UTXBRKTransmit Shift Register Status bit (PIC18F)TRMTTRMTTransmit Shift Register Empty bit (read-only, PIC24F)Transmit Enable bit TXEN UTXENEUSART Transmit Interrupt Flag bit/UARTx TransmitterTXIFUxTXIFInterrupt Flag Status bit9th bit of Transmit Data TX9D UxTXREG(word write needed)Wake-up Enable bit/Wake-up on Start bit Detect duringSleep Mode Enable bitWUEWAKEUNSUPPORTED PIC18F FEATURESThe following are PIC18F EUSART features that arenot supported by the newer PIC24F UART module:• FOSC/[64 (n + 1)] baud rate.• Synchronous Master and Slave Communicationmodes are not supported in the PIC24F UART. Touse Synchronous mode in PIC24F devices, usethe SPI module.• The PIC18F EUSART option of changingbetween low speed and high speed by changingthe BRGH bit between ‘0’ and ‘1’ is not supportedin PIC24F. The target will need to change thebaud rate for PIC24F.© 2006 Microchip Technology Inc. DS39764A-page 39
Page 1 and 2: PIC18F to PIC24F Migration: An Over
Page 3 and 4: W REGISTERSAll PIC18F devices have
Page 5 and 6: SUPPORTED DATA TYPESAside from bit-
Page 7 and 8: Memory Map and Program MemoryBoth P
Page 9 and 10: INTERRUPT/RESET/TRAP VECTORSIn PIC1
Page 11 and 12: Data Memory SpaceThe PIC24F data me
Page 13 and 14: Resets and Start-up TimingThe PIC24
Page 15 and 16: ADDITIONAL PIC24F RESETSBeyond the
Page 17 and 18: Interrupt ControllerThe PIC24F inte
Page 19 and 20: OscillatorThe PIC24F oscillator sys
Page 21 and 22: INTERNAL RC OSCILLATORS (INTOSC/FRC
Page 23 and 24: Power-Saving FeaturesPIC24F power-s
Page 25: Watchdog Timer (WDT)The Watchdog Ti
Page 28 and 29: NEW PIC24F FEATURES• Open-drain i
Page 30 and 31: NEW PIC24F FEATURESThe most apparen
Page 32 and 33: In Full-Bridge mode, the PIC18F PWM
Page 34 and 35: Serial Peripheral Interface (SPI)Th
Page 36 and 37: Inter-Intergrated Circuit (I 2 C)Th
Page 40 and 41: TRANSMISSION SETUP (8-BIT DATA MODE
Page 42 and 43: NEW PIC24F A/D FEATURESMany of the
Page 44 and 45: NEW PIC24F COMPARATOR MODULEFEATURE
Page 46 and 47: NOTES:DS39764A-page 46© 2006 Micro
Page 48 and 49: TABLE A-1:PIC18FInstructionPIC18F A
Page 54: WORLDWIDE SALES AND SERVICEAMERICAS

PIC18F to PIC24F Migration: An Overview - Microchip

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