TWO-SPEED START-UPTwo-Speed Start-up is implemented identically in<strong>PIC18F</strong> and <strong>PIC24F</strong> devices. In both cases, the featureis controlled by the IESO Configuration bit.FAIL-SAFE CLOCK MONITORThe Fail-Safe Clock Moni<strong>to</strong>r feature is also available forthe <strong>PIC24F</strong>. It is controlled, along with run-time clockswitching, by the Configuration Word bits,FCKSM1:FCKSM0 (CW2). FSCM in <strong>PIC24F</strong>devices is similar <strong>to</strong> the <strong>PIC18F</strong> implementation byau<strong>to</strong>matically switching <strong>to</strong> the FRC when the primaryoscilla<strong>to</strong>r s<strong>to</strong>ps.The single significant difference is the secondaryeffects of an FSCM event. For <strong>PIC18F</strong> devices, aprimary oscilla<strong>to</strong>r failure sets the OSCFIF interrupt flagbit, which can optionally generate a device interrupt.For <strong>PIC24F</strong> devices, an FSCM event sets both the CFflag (OSCCON) and OSCFAIL (INTCON1) bits,and generates an unmaskable hardware trap whichthen must be cleared.MIGRATING A TYPICAL APPLICATION• Most applications built on a <strong>PIC18F</strong> device withnanoWatt Technology will be able <strong>to</strong> use the sameoscilla<strong>to</strong>r type and clock frequency when a<strong>PIC24F</strong> device is substituted. This is particularlytrue when the oscilla<strong>to</strong>r uses a crystal (HS modeor XT mode, between 3.5 and 10 MHz), anexternal clock genera<strong>to</strong>r or the internal RCoscilla<strong>to</strong>r block.• <strong>PIC18F</strong> applications that use a 32 kHz crystal forthe primary oscilla<strong>to</strong>r will need <strong>to</strong> use thesecondary oscilla<strong>to</strong>r for their <strong>PIC24F</strong> equivalentversions. The crystal circuit will need <strong>to</strong> be moved<strong>to</strong> the T1OSCI/T1OSCO pins, and the SecondaryOscilla<strong>to</strong>r mode (SOSC) will need <strong>to</strong> be selectedas the start-up clock source.• <strong>PIC18F</strong> applications using an External RCPrimary Oscilla<strong>to</strong>r mode, or an XT Oscilla<strong>to</strong>rmode running below 3.5 MHz, must now use theFRC oscilla<strong>to</strong>r as the default clock source.Configuration will need <strong>to</strong> be changed <strong>to</strong> selectFRC as the default start-up clock source.• If clock switching is used, the clock switchsequences will need <strong>to</strong> be added. These aredescribed in the appropriate device data sheet.MIGRATION CONSIDERATIONSWhen migrating <strong>to</strong> a <strong>PIC24F</strong> microcontroller (or anymicrocontroller, for that matter), any application that isbased on a crystal clock source should be re-evaluatedfor oscilla<strong>to</strong>r operation and stability. It is important <strong>to</strong>verify that the crystal performance is reliable across thevoltage, temperature and process variationsanticipated for the application.For more information, refer <strong>to</strong> the application noteslisted in the “References” section on page 45.DS39764A-page 22© 2006 <strong>Microchip</strong> Technology Inc.
Power-Saving Features<strong>PIC24F</strong> power-saving features are very similar <strong>to</strong> thePower-Saving modes offered in <strong>PIC18F</strong> nanoWattTechnology devices. Both architectures includerun-time switching of system clock sources, Idle andSleep modes, and hardware invoked exits throughResets and interrupts. <strong>PIC24F</strong> devices describe thesefeatures in a somewhat different manner, and supportadditional features for strategic reduction of powerconsumption.A comparison of the power-saving features in botharchitectures is presented in Table 16.Note:For the sake of brevity, references <strong>to</strong>“<strong>PIC18F</strong>” throughout this section shouldbe interpreted as meaning “<strong>PIC18F</strong>devices with nanoWatt Technology”.TABLE 16:COMPARISON BETWEEN <strong>PIC18F</strong> AND <strong>PIC24F</strong> POWER-SAVING FEATURESFeature Description <strong>PIC18F</strong> <strong>PIC24F</strong>Run-Time Clock Switching Yes YesPower-Saving Mode Invocation Instruction and hardware bit setting Instruction with argumentIdle ModeSelective Peripheral IdleSleep Mode Yes YesDoze Mode No YesPMD Option No YesYesNoYesYesRUN-TIME CLOCK SWITCHING<strong>PIC18F</strong> and <strong>PIC24F</strong> devices have all the same types ofsystem clock sources (primary, secondary and internaloscilla<strong>to</strong>r). In addition, Sleep and Idle modes aredefined in the same manner. The difference betweenthe devices is strictly terminology: <strong>PIC24F</strong> devices donot use the Power-Managed mode terminology createdfor nanoWatt Technology. Because oscilla<strong>to</strong>r modeswitching in more expansive in <strong>PIC24F</strong> devices, the old<strong>PIC18F</strong> descriptions of Power-Managed modes(PRI_RUN, SEC_IDLE, etc.) are no longer used. However,completely equivalent modes are available in<strong>PIC24F</strong> devices; that is, using the NOSC2:NOSC0 bits<strong>to</strong> select the FRC oscilla<strong>to</strong>r as the clock source isequivalent <strong>to</strong> switching <strong>to</strong> RC_RUN mode in a <strong>PIC18F</strong>device.In <strong>PIC18F</strong> devices, clock switching is accomplished bywriting <strong>to</strong> the SCS1:SCS0 bits (OSCCON). For<strong>PIC24F</strong> devices, clock switching is accomplished bywriting <strong>to</strong> the NOSC2:NOSC0 bits, accompanied by asafety unlock procedure (see the “Oscilla<strong>to</strong>r” sectionon page 19 for more details). In addition, clock switchingcan be disabled entirely by setting Configuration bit,FCKSM1 (CW2).The internal transitions between clock sources areessentially the same in both architectures and areaccompanied by similar delays.SLEEP AND IDLE MODES<strong>PIC18F</strong> devices use the SLEEP instruction <strong>to</strong> invoketheir Power-Managed (x_IDLE and Sleep) modes. Theactual mode invoked is determined by the IDLEN bit(OSCCON); an Idle mode is entered when the bit isset or Sleep mode when the bit is cleared.In <strong>PIC24F</strong> devices, the equivalent instruction isPWRSAV. The instruction is used with an argument(either symbolic or literal) <strong>to</strong> specify the desired mode.As before, Idle mode is invoked when the literalargument is ‘1’, and Sleep mode when it is ‘0’.SELECTIVE PERIPHERAL IDLINGIn <strong>PIC18F</strong> devices, Idle mode is an all-or-nothing affair;all peripherals remain operational during an Idle mode.In <strong>PIC24F</strong> devices, peripherals can be selectivelydisabled during Idle mode. Most peripheral moduleshave a control bit, xxxIDL (where ‘xxx’ represents theperipheral mnemonic), that determines if the peripheralcontinues operation when Idle mode is invoked. TheIDL bits allow modules <strong>to</strong> be partially powered down,providing for additional incremental power savings.EXITING POWER-SAVING MODESExiting a Power-Managed mode can be achieved by anenabled interrupt or by a Reset. A WDT Reset or interruptexits the Power-Managed mode and returns thedevice <strong>to</strong> the previous clock source. All other methodsswitch the controller <strong>to</strong> the 8 MHz FRC internal oscilla<strong>to</strong>r,if Two-Speed Start-up is enabled, until the primary clocksource is ready.© 2006 <strong>Microchip</strong> Technology Inc. DS39764A-page 23