12.07.2015 Views

PIC18F to PIC24F Migration: An Overview - Microchip

PIC18F to PIC24F Migration: An Overview - Microchip

PIC18F to PIC24F Migration: An Overview - Microchip

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

TWO-SPEED START-UPTwo-Speed Start-up is implemented identically in<strong>PIC18F</strong> and <strong>PIC24F</strong> devices. In both cases, the featureis controlled by the IESO Configuration bit.FAIL-SAFE CLOCK MONITORThe Fail-Safe Clock Moni<strong>to</strong>r feature is also available forthe <strong>PIC24F</strong>. It is controlled, along with run-time clockswitching, by the Configuration Word bits,FCKSM1:FCKSM0 (CW2). FSCM in <strong>PIC24F</strong>devices is similar <strong>to</strong> the <strong>PIC18F</strong> implementation byau<strong>to</strong>matically switching <strong>to</strong> the FRC when the primaryoscilla<strong>to</strong>r s<strong>to</strong>ps.The single significant difference is the secondaryeffects of an FSCM event. For <strong>PIC18F</strong> devices, aprimary oscilla<strong>to</strong>r failure sets the OSCFIF interrupt flagbit, which can optionally generate a device interrupt.For <strong>PIC24F</strong> devices, an FSCM event sets both the CFflag (OSCCON) and OSCFAIL (INTCON1) bits,and generates an unmaskable hardware trap whichthen must be cleared.MIGRATING A TYPICAL APPLICATION• Most applications built on a <strong>PIC18F</strong> device withnanoWatt Technology will be able <strong>to</strong> use the sameoscilla<strong>to</strong>r type and clock frequency when a<strong>PIC24F</strong> device is substituted. This is particularlytrue when the oscilla<strong>to</strong>r uses a crystal (HS modeor XT mode, between 3.5 and 10 MHz), anexternal clock genera<strong>to</strong>r or the internal RCoscilla<strong>to</strong>r block.• <strong>PIC18F</strong> applications that use a 32 kHz crystal forthe primary oscilla<strong>to</strong>r will need <strong>to</strong> use thesecondary oscilla<strong>to</strong>r for their <strong>PIC24F</strong> equivalentversions. The crystal circuit will need <strong>to</strong> be moved<strong>to</strong> the T1OSCI/T1OSCO pins, and the SecondaryOscilla<strong>to</strong>r mode (SOSC) will need <strong>to</strong> be selectedas the start-up clock source.• <strong>PIC18F</strong> applications using an External RCPrimary Oscilla<strong>to</strong>r mode, or an XT Oscilla<strong>to</strong>rmode running below 3.5 MHz, must now use theFRC oscilla<strong>to</strong>r as the default clock source.Configuration will need <strong>to</strong> be changed <strong>to</strong> selectFRC as the default start-up clock source.• If clock switching is used, the clock switchsequences will need <strong>to</strong> be added. These aredescribed in the appropriate device data sheet.MIGRATION CONSIDERATIONSWhen migrating <strong>to</strong> a <strong>PIC24F</strong> microcontroller (or anymicrocontroller, for that matter), any application that isbased on a crystal clock source should be re-evaluatedfor oscilla<strong>to</strong>r operation and stability. It is important <strong>to</strong>verify that the crystal performance is reliable across thevoltage, temperature and process variationsanticipated for the application.For more information, refer <strong>to</strong> the application noteslisted in the “References” section on page 45.DS39764A-page 22© 2006 <strong>Microchip</strong> Technology Inc.

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!