PIC18F to PIC24F Migration: An Overview - Microchip

APPENDIX A:MAPPING PIC18FTO PIC24FINSTRUCTIONSThis section describes how PIC18F assembly instructionsmap to PIC24F assembly instructions. Keep inmind that the addressing structure of the two productlines has changed and this will affect how many ofthese instructions are mapped. See the “AddressingModes” section on page 5 of this document for moredetails on the different addressing modes. The mappingprovided does not cover all possible permutationsof the different addressing modes. Please be awarethat if indirect addressing is available for an instruction,a single example is provided in the mapping chart. Alsonote that this chart only maps PIC18F instructions toPIC24F instructions. It does not highlight many of thenew capabilities of the PIC24F product line.Below is a description of the differences in notation ofthe instruction sets between the two product lines.Key:Wn, Ws, Wb and Wd: any of the working registers. ForPIC24F, WREG refers exclusively to W0.[Ws]: use Ws as a pointer; similar to using INDF0 inPIC18F.[Ws++]: use Ws as a pointer and increment it afteraccessing the variable it points to. Similar to usingPOSTINC0 in PIC18F.[Ws + Wd]: use Ws as a pointer and Wd as an offsetto the pointer. Similar to using PLUSW0 in PIC18F..B or .D: immediately following an instructionmnemonic indicates that the instruction will operate ona byte or double word (4 bytes), rather than a word(2 bytes).Varn: the address of a variable n in data memory space.#litn: a literal value of length n.Expr: an address in program memory space.TABLE A-1:PIC18FInstructionPIC18F ASSEMBLY INSTRUCTIONS AND THEIR PIC24F EQUIVALENTSPIC18F Example(s)PIC24F EquivalentInstruction(s)NotesADDFSR ADDFSR 0, #lit6 ADD #lit10, Wn 1) This is part of the extended instructionset and may not be available on allPIC18F devices.2) Most W registers can be used asindirect pointers (see “AddressingModes” section on page 5).ADDLW ADDLW #lit8 ADD #lit10, WnADDULNK (1) ADDULNK#lit6 LNK #lit14ADDWF ADDWF var1, w ADD var1, WREG This instruction can only operate on W0.ADDWF var1, f ADD var1 This instruction can only operate on W0.ADDWF INDF0, w ADD Wb, [Ws], WbADDWF INDF0, f ADD Wb, [Ws], [Ws]ADDWFC ADDWF var1, w ADDC var1, WREG This instruction can only operate on W0.ADDWF var1, f ADDC var1 This instruction can only operate on W0.ADDWF INDF0, w ADDC Wb, [Ws], WbADDWF INDF0, f ADDC Wb, [Ws], [Ws]ANDLW ANDLW #lit8 AND #lit10, Wn Wn = Wn OR #lit10.AND Wb, #lit5, Wd Wd = Wb OR #lit5.ANDWF ANDWF var1, w AND var1, WREG This instruction can only operate on W0.ANDWF var1, f AND var1 This instruction can only operate on W0.ANDWF INDF0, w AND Wb, [Ws], WbANDWF INDF0, f AND Wb, [Ws], [Ws]BC BC Expr BRA C, ExprBCF BCF var1, #lit3 BCLR var1, #lit4BCLR Ws, #lit4BCF INDF0, #lit3 BCLR [Ws], #lit4Note 1: This instruction is part of the PIC18F extended instruction set. It is not available in earlier PIC18F devicesor PIC18F devices operating in Legacy mode (XINST Configuration bit is unprogrammed).© 2006 Microchip Technology Inc. DS39764A-page 47