PIC18F to PIC24F Migration: An Overview - Microchip

INTERNAL RC OSCILLATORS (INTOSC/FRCAND INTRC/LPRC)The internal oscillators for PIC18F devices withnanoWatt Technology and PIC24F devices are virtuallyidentical, except in name. Both feature two independentinternal oscillators, an efficient 31 kHz oscillator and anaccurate, high-speed 8 MHz oscillator. Both architecturesuse a configurable postscaler, driven by the 8 MHzsource, to provide a range of clock frequencies, from31 kHz to 4 MHz (as well as the undivided 8 MHzoutput). Both architectures allow software selection fromthe 31 kHz or 8 MHz oscillators to provide the 31 kHzsource for various system features. Both clock systemspermit tuning of the 8 MHz source through a nominalrange of ±12%.The differences here are minor. For PIC18F devices,the internal 31 kHz and 8 MHz sources are generallyreferred to as INTOSC and INTRC. For PIC24Fdevices, they are known as the Fast RC (FRC) andLow-Power RC (LPRC) oscillators. INTOSC/FRC tuningis accomplished with 5 tuning bits (TUN4:TUN0) inPIC18F devices; PIC24F devices use 6 tuning bits(TUN5:TUN0) for finer resolution. Finally, the defaultvalue on Reset for the 8 MHz postscaler is 1 MHz forPIC18F devices and 4 MHz for PIC24F devices.PLL FREQUENCY MULTIPLIERPIC18F and PIC24F devices both support a 4x PLLfrequency multiplier for use with select clock sources.In all cases, the PLL provides a stable output only whenthe input frequency is between 4 and 10 MHz. Theoperation of the PLL differs substantially between thetwo architectures.For most PIC18F devices incorporating nanoWattTechnology, the PLL is automatically enabled forspecific, primary oscillator configurations and is alwaysoperational. All devices can use the HS oscillator withthe PLL; select later devices also allow the use of thePLL with the EC mode. These are distinct primaryoscillator configurations. If the user wishes to disable thePLL, the device must be reprogrammed and reconfigured.If the internal oscillator block is selected as thedevice’s default oscillator, the PLL is made availablewhen the INTOSC postscaler is configured for an outputof 4 or 8 MHz. In these cases, the PLL can be selectivelyenabled under software control with the PLLEN controlbit (OSCTUN).For PIC24F devices, the PLL is always available undersoftware control. It is available for all primary oscillatormodes, as well as FRC or FRCDIV operation (as longas a postscaler output of at least 4 MHz is selected). Touse the PLL, it is only necessary to perform a clockswitch to one of the PLL Clock modes. Once a PLLmode is selected, the state of the PLL’s output stabilityis indicated by the flag bit, LOCK (OSCCON).When the bit is set, the PLL output is stable.CLOCK SWITCHINGClock switching differs significantly between PIC18Fand PIC24F devices. Conceptually, both architectureshave three categories of oscillators: primary (externalcomponents connected to OSC pins), secondary(external crystal connected to T1OSC or SOSC pins)and internal RC. PIC18F devices permit the definitionof one and only one primary oscillator type used duringdevice configuration. This is the oscillator that is alwaysused when on device power-up and Reset. Thereafter,the device can switch between primary, secondary andinternal oscillator sources, under software control, bywriting to the SCS1:SCS0 bits. Once a primaryoscillator is defined, it cannot be changed unless thedevice is reprogrammed.For PIC24F devices, any one of the three major clocksources can be configured as the default start-up oscillator;users are no longer confined to just the primaryoscillator sources. During run time, the device canswitch between any of the available oscillator modesunder software control. This means, that among otherthings, it is possible to switch between a Primary Clockmode and its PLL counterpart while the application isrunning. It is also possible to start the device using theTimer1 or LPRC oscillator, rather than switch to thosesources after Reset or power-up (as was required inPIC18F implementations of nanoWatt Technology). Infact, it is possible to completely disable the primaryoscillator source in PIC24F devices; something thatcannot be done on the PIC18F architecture.This increased flexibility makes clock switching onPIC24F devices a more complex sequence. The newoscillator is selected with the NOSC2:NOSC0 bits andby setting the Oscillator Switch Enable bit, OSWEN. Toprevent unintended changes, PIC24F devices also usean additional safety interlock that requires an unlocksequence to write each byte of the OSCCON register.PIC24F unlocks the high or low byte for one instructionafter two specific literals are written to the high or lowbyte of OSCCON. An instruction counter ensures theunlock sequence is performed within a maximumnumber of instructions and remains unlocked for oneinstruction cycle. Because these sequences are sotime critical, the unlock sequences are done with anassembly language routine. When the NOSC bitsmatch the COSC bits, or the OSWEN bit is clear, theclock switch has been completed successfully.Because the New Oscillator Select bits, NOSC, andOscillator Switch Enable bit, OSWEN (OSCCON),reside in opposite halves of OSCCON, two unlocksequences are needed to request a system clockswitch. For examples of the OSCCON unlocksequences, refer to the specific device data sheet.© 2006 Microchip Technology Inc. DS39764A-page 21