TMS320F206 Digital Signal Processor (Rev. A) - Futurlec

TMS320F206DIGITAL SIGNAL PROCESSORSPRS050A – NOVEMBER 1996 – REVISED APRIL 1998architectural overviewThe ’F206 advanced Harvard-type architecture maximizes the processing power by maintaining two separatememory bus structures — program and data — for full-speed execution. The multiple buses allow data andinstructions to be read simultaneously. Instructions support data transfers between the two spaces. Thisarchitecture permits coefficients stored in program memory to be read in RAM, eliminating the need for aseparate coefficient ROM. This, coupled with a four-deep pipeline, allows the TMS320F206 to execute mostinstructions in a single cycle.status and control registersTwo status registers, ST0 and ST1, contain the status of various conditions and modes. These registers canbe stored into data memory and loaded from data memory, thereby allowing the status of the machine to besaved and restored for subroutines.The load-status-register (LST) instruction is used to write to ST0 and ST1. The store-status-register (SST)instruction is used to read from ST0 and ST1 (except the INTM bit, which is not affected by the LST instruction).The individual bits of these registers can be set or cleared when using the SETC and CLRC instructions. Table 3and Table 4 show the organization of status registers ST0 and ST1, indicating all status and control bitscontained in each. Several bits in the status registers are reserved and read as logic 1s. Refer to Table 5 forstatus-register field definitions.Table 3. Status and Control Register Zero15 13 12 11 10 9 8 7 6 5 4 3 2 1 0ST0 ARP OV OVM 1 INTM DPTable 4. Status and Control Register One15 13 12 11 10 9 8 7 6 5 4 3 2 1 0ST1 ARB CNF TC SXM C 1 1 1 1 XF 1 1 PM10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443