TMS320F206 Digital Signal Processor (Rev. A) - Futurlec

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TMS320F206DIGITAL SIGNAL PROCESSORSPRS050A – NOVEMBER 1996 – REVISED APRIL 1998PZ PACKAGE( TOP VIEW )EMU0EMU1 / OFFTCKTRSTTDITMSTDOV SSCLKRFSRDRCLKXV SSFSXDXV DDTOUTTXV SSRXIO0IO1XFBIORS76777879808182838485868788899091929394959697989910075 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 511 2 3 4 5 6 7 8 95049484746454443424140393837363534333231302928272610 11 12 13 14 15 16 17 18 19 20 2122 23 24 25V DDREADYV SSR/WSTRBRDWEBRV SSD15D14D13D12V SSD11V DDD10D9D8D7V SSD6D5D4D3TESTMP / MCDIV1V CCPDIV 2HOLDAVIO2IO3PLL5VCLKIN/X2X1V SSCLKOUT1VCCPNMIHOLD / INT1INT2INT3VDDVDDVSSD0D1D2SSVVV DDA15A14A13A12SSA11A10A9A8A7VA6A5A4VA3A2A1A0VPSISDSSSDDSSSSTable 1 shows the capacity of on-chip RAM and ROM, the number of serial and parallel I/O ports, the executiontime of one machine cycle, and the type of package with total pin count of the TMS320F206 device.DEVICEDATARAMTable 1. Characteristics of the TMS320F206 ProcessorON-CHIP MEMORYDATA/PROGROMFLASHEEPROMI/O PORTSPROG PROG SERIAL PARALLELPOWER CYCLE PACKAGESUPPLY TIME TYPE WITH(V) (ns) PIN COUNTTMS320F206 288 4K + 256 – 32K 2 64K 5 50 100-pin TQFP2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F206DIGITAL SIGNAL PROCESSORD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0TERMINALNAME NO.4140393836343332312928272624232274737271696867666462616058575655TYPE†I/O/ZO/ZTMS320F206 Terminal FunctionsDESCRIPTIONSPRS050A – NOVEMBER 1996 – REVISED APRIL 1998DATA AND ADDRESS BUSESParallel data bus D15 [most significant bit (MSB)] through D0 [least significant bit (LSB)]. D15–D0 areused to transfer data between the TMS320F206 and external data / program memory or I / O devices.Placed in the high-impedance state when not outputting (R / W high) or RS when asserted. They go intothe high-impedance state when OFF is active low.Parallel address bus A15 (MSB) through A0 (LSB). A15–A0 are used to address external data / programmemory or I / O devices. These signals go into the high-impedance state when OFF is active low.MEMORY CONTROL SIGNALSPS 53 O/ZProgram-select signal. PS is always high unless low-level asserted for communicating to off-chip programspace. PS goes into the high-impedance state when OFF is active low.DS 51 O/ZData-select signal. DS is always high unless low-level asserted for communicating to off-chip programspace. DS goes into the high-impedance state when OFF is active low.IS 52 O/ZI / O space-select signal. IS is always high unless low-level asserted for communicating to I/O ports. ISgoes into the high-impedance state when OFF is active low.READY 49 IData-ready input. READY indicates that an external device is prepared for the bus transaction to becompleted. If the external device is not ready (READY low), the TMS320F206 waits one cycle and checksREADY again. If READY is not used, it should be pulled high.R/W 47 O/ZRead/write signal. R / W indicates transfer direction when communicating with an external device. R/Wis normally in read mode (high), unless low level is asserted for performing a write operation. R / W goesinto the high-impedance state when OFF is active low.RD 45 O/ZRead-select indicates an active, external read cycle. RD is active on all external program, data, and I / Oreads. RD goes into the high-impedance state when OFF is active low. The function of the RD pin canbe programmed to provide an inverted R/W signal instead of RD. The FRDN bit (bit 15) in the PMSTregister controls this selection.† I = input, O = output, Z = high impedance, PWR = power, GND = groundPOST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–14433
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TMS320F206 Digital Signal Processor (Rev. A) - Futurlec

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