TMS320F206 Digital Signal Processor (Rev. A) - Futurlec

TMS320F206DIGITAL SIGNAL PROCESSORSPRS050A – NOVEMBER 1996 – REVISED APRIL 1998addressing modes (continued)There are seven types of indirect addressing: autoincrement or autodecrement, postindexing by either addingor subtracting the contents of AR0, single indirect addressing with no increment or decrement, and bit-reversedaddressing [used in Fast Fourier Transforms (FFTs)] with increment or decrement. All operations are performedon the current auxiliary register in the same cycle as the original instruction, following which the current auxiliaryregister and ARP can be modified.In immediate addressing, the actual operand data is provided in a portion of the instruction word or words. Thereare two types of immediate addressing: long and short. In short-immediate addressing, the data is containedin a portion of the bits in a single-word instruction. In long-immediate addressing, the data is contained in thesecond word of a two-word instruction. The immediate-addressing mode is useful for data that does not needto be stored or used more than once during the course of program execution, such as initialization values,constants, etc.The register-addressing mode uses operands in CPU registers either explicitly, such as with a direct referenceto a specific register, or implicitly with instructions that intrinsically reference certain registers. In either case,operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operandaddress or immediate value.repeat featureThe repeat function can be used with instructions (as defined in Table 13) such as multiply/accumulates (MACand MACD), block moves (BLDD and BLPD), I/O transfers (IN/OUT), and table read/writes (TBLR/TBLW).These instructions, although normally multicycle, are pipelined when the Repeat feature is used, and theyeffectively become single-cycle instructions. For example, the table-read instruction may take three or morecycles to execute, but when the instruction is repeated, a table location can be read every cycle.When using the repeat feature, the repeat counter (RPTC) is loaded with the addressed data memory locationif direct or indirect addressing is used, or an 8-bit immediate value if short-immediate addressing is used. TheRPTC register is loaded by the RPT instruction. This results in a maximum of N + 1 executions of a giveninstruction, when RPTC is loaded with N. RPTC is cleared by reset. Once a repeat instruction (RPT) is decoded,all interrupts, including NMI (except reset), are masked until the completion of the repeat loop.instruction set summaryThis section summarizes the opcodes of the instruction set for the ’F206 digital signal processor (DSP). Thisinstruction set is a superset of the ’C1x and ’C2x instruction sets. The instructions are arranged according tofunction and are alphabetized by mnemonic within each category. The symbols in Table 12 are used in theinstruction set summary table (Table 13). The Texas Instruments ’C20x assembler accepts ’C2x instructions.The number of words that an instruction occupies in program memory is specified in column 3 of Table 13.Several instructions specify two values separated by a slash mark (/) for the number of words. In these cases,different forms of the instruction occupy a different number of words. For example, the ADD instruction occupiesone word when the operand is a short-immediate value or two words if the operand is a long-immediate value.The number of cycles that an instruction requires to execute is in column 3 of Table 13. All instructions areassumed to be executed from internal program memory (RAM) and internal data dual-access memory. Thecycle timings are for single-instruction execution, not for repeat mode.26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443