TMS320F206 Digital Signal Processor (Rev. A) - Futurlec

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<strong>TMS320F206</strong>DIGITAL SIGNAL PROCESSORSPRS050A – NOVEMBER 1996 – REVISED APRIL 1998PARAMETER MEASUREMENT INFORMATIONFigure 5 shows the TTL-level inputs.2.0 V90%10%0.8 VFigure 5. TTL-Level InputsTTL-compatible input transition times are specified as follows: For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90%of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltagerange and lower. For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10%of the total voltage range and higher and the level at which the input is said to be high is 90% of the totalvoltage range and higher.38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
<strong>TMS320F206</strong>DIGITAL SIGNAL PROCESSORPARAMETER MEASUREMENT INFORMATIONSPRS050A – NOVEMBER 1996 – REVISED APRIL 1998timing parameter symbologyTiming parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten thesymbols, some of the pin names and other related terminology have been abbreviated as follows:A Address or A [15:0] M Address, data, and control signals:(A, D, MS, S, BR, RD, W, and R/W)CI CLKIN/X2 MS Memory strobe pins IS, DS, or PSCLKR Serial-port receive clock R READYCLKX Serial-port transmit clock RD Read cycle or RDCO CLKOUT1 RS RESET pins RS or RSD Data or D [15:0] S STRB or SynchronousFR FSR TP Transitory phaseFX FSX W Write cycle or WEH HOLDHA HOLDAIN INTN; BIO, INT1 –INT3, NMIIO IOx : IO0, IO1, IO2, or IO3Lowercase subscripts and their meanings are:The following letters and symbols and their meanings are:a access time H Highc cycle time (period) L Lowd delay time IV Invaliddis disable time HZ High impedanceen enable time X Unknown, changing, or don’t care levelffall timehhold timerrise timesu setup timettransition timevvalid timewpulse duration (width)general notes on timing parametersAll output signals from the TMS320x20x devices (including CLKOUT1) are specified from an internal clock suchthat all output transitions for a given half cycle occur with a minimum of skewing relative to each other.The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.For actual cycle examples, refer to the appropriate cycle description section of this data sheet.POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–144339
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TMS320F206 Digital Signal Processor (Rev. A) - Futurlec

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