TMS320F206 Digital Signal Processor (Rev. A) - Futurlec

TMS320F206DIGITAL SIGNAL PROCESSORSPRS050A – NOVEMBER 1996 – REVISED APRIL 1998timing @ V DD = 5 V with the PLL circuit enabledPARAMETER TEST CONDITIONS MIN MAX UNITInput clock frequency, multiply-by-one mode 4† 20.48fx Input clock frequency, multiply-by-two mode TA = –40°C to 85°C, 5 V 4† 10.24 MHzInput clock frequency, multiply-by-four mode 4† 5.12† Values specified from characterization data and not testedswitching characteristics over recommended operating conditions (see Figure 8) [H = 0.5t c(CO) ]PARAMETER’320F206-40MIN TYP MAXtc(CO) Cycle time, CLKOUT1 48.8 250 nstf(CO) Fall time, CLKOUT1† 5 nstr(CO) Rise time, CLKOUT1† 5 nstw(COL) Pulse duration, CLKOUT1 low‡ H – 3 H H + 1 nstw(COH) Pulse duration, CLKOUT1 high‡ H – 1 H H + 3 nstd(TP) Delay time, transitory phase—PLL synchronized after CLKIN supplied 2500 cycles† Values specified from characterization data and not tested‡ Values specified from design data and not testedUNITtiming requirements over recommended operating conditions (see Figure 8)Cycle time, CLKIN multiply-by-one mode 48.8’320F206-40tc(CI) ( Cycle time, CLKIN multiply-by-two mode 97.7 nsCycle time, CLKIN multiply-by-four mode 195.3tf(CI) Fall time, CLKIN† 4 nstr(CI) Rise time, CLKIN† 4 nstw(CIL) Pulse duration, CLKIN low 21 125 nstw(CIH) Pulse duration, CLKIN high 21 125 ns† Values specified from characterization data and not testedtw(CIH)MINMAXUNITtc(CI)tw(CIL)CLKINtf(CI)tc(CO)tw(COH)tw(COL)tf(CO)tr(CO)tr(CI)CLKOUT1Figure 8. CLKIN-to-CLKOUT1 Timing With PLL (Enabled)42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443