ARCHIVE 2009 - BiTS Workshop

2009Session 3ARCHIVE 2009ADVENTURES IN TEST & BURN-IN OPERATIONSParallel Logic Test Interface SolutionsYH Jeon, Sang-Il Kwon—TSEGary Westendorf, Chris Mack—PragmaticsCID: A New Breakthrough Solution For Contactor Hardware TrackingJonathan Mondero—Texas Instruments PhilippinesKevin Tiernan, Mike Guenther—Texas Instruments HoustonEugene Batilo—Everett Charles Technologies – STG SingaporeMechanical Reliability Test as Part of Final Test of a Packaged ChipChe-Yu Li, Tia Korhonen—Che-Yu Li & Co.Tim Wooden—Protos ElectronicsSM Low—ADE TechnologiesSubstrate Bias: Application in Final Test and Burn-in of High-PowerCPU'sMax Paransky—Texas InstrumentsCOPYRIGHT NOTICEThe papers in this publication comprise the proceedings of the 2007 BiTS Workshop. They reflect theauthors’ opinions and are reproduced as presented , without change. Their inclusion in this publicationdoes not constitute an endorsement by the BiTS Workshop, the sponsors, BiTS Workshop LLC, or theauthors.There is NO copyright protection claimed by this publication or the authors. However, each presentationis the work of the authors and their respective companies: as such, it is strongly suggested that any usereflect proper acknowledgement to the appropriate source. Any questions regarding the use of anymaterials presented should be directed to the author/s or their companies.All photographs in this archive are copyrighted by BiTS Workshop LLC. The BiTS logo and ‘Burn-in &Test Socket Workshop’ are trademarks of BiTS Workshop LLC.BiTS Workshop 2009 Archive

2009Session 3Adventures in Test & Burn-in OperationsParallel Logic TestInterface SolutionsYH Jeon, TSESang-Il Kwon, TSEChris Mack, PragmaticsGary Westendorf, Pragmatics2009 BiTS WorkshopMarch 8 - 11, 2009Contents• Welcome & Introductions• Why We Chose This Subject• Enabling Technologies• Logic / SOC Test Interfaces• Fan-Out Methodologies• Fan-Out Signal Performance• Considerations• Conclusion3/2009 Parallel Logic Test Interface Solutions2Paper #1March 8 - 11, 20091

2009Session 3Adventures in Test & Burn-in OperationsWhy We Chose This Subject…• Lessons learned from years ofproducing high parallel memory &MCP test interfaces are being appliedto production Logic / SOC testing.• Economics often require Logic / SOCproduction test without new capitalspending on ATE.• The real estate inside parallel testinterfaces can be utilized to expandATE resources.• There are more Logic / SOC devicesemerging that require high volumeproduction.3/2009 Parallel Logic Test Interface Solutions3Enabling Technologies• Increasing density ATE PEs & interconnects.• DFT/BIST/SCAN reduces ATE I/O requirements.• Logic load boards are transitioning to paralleltest interfaces with real estate for fan-outcircuitry & additional DUT power supplies.• Advancements in lithography & packagingprovides denser, smaller Logic / SOC devicesthat can be handled by memory test handlers.3/2009 Parallel Logic Test Interface Solutions4Paper #1March 8 - 11, 20092

2009Session 3Adventures in Test & Burn-in OperationsOne-Piece PCB Logic Load Board• Planarity & contact issues• Poor thermal performance• Limited real estate for additional circuitryTest SocketsLoad Board• PCB size limitations for high parallelism• PCB aspect ratio limitations for fine pitch applications• Costly PCB design & layout costs for high density &high speed performance• PCB yield & cost issues for high density & performance• Very limited repair & maintenance options3/2009 Parallel Logic Test Interface Solutions5New Test Interface Technology• Extensive real estate for additional circuitry• Excellent tri-temp thermal performance• Excellent planarity & contact16 DUT800MHz• Excellent impedance control• Small PCB size• Enables high parallelism• Reduces PCB yield loss• Improves aspect ratio for fine pitch applications• Modular structure provides repair options3/2009 Parallel Logic Test Interface Solutions6Paper #1March 8 - 11, 20093

2009Session 3Adventures in Test & Burn-in OperationsStructure of New Logic Test InterfaceIndividual Test SocketsIndividual Sockets PCBsSpring Towersfor Isolationand FloatCoax InterconnectSystem InsideProtective HousingConnectorsfor TH Connection3/2009 Parallel Logic Test Interface Solutions7Structure of New Logic Test InterfaceTest SocketSocket PCBVertical PCBCable or ConnectorTerminationRealEstateCloseTo DUTBothSides!!3/2009 Parallel Logic Test Interface Solutions8Paper #1March 8 - 11, 20094

2009Session 3Adventures in Test & Burn-in OperationsTwo Y Driver SharingATE Base Board DUT Socket PCB DUT Design100ohm50ohmL1T/L matchingDUT1(+/- 0.1mm)DriverCoaxial cable100ohmL2DUT2L1 = L2Resource Share X 23/2009 Parallel Logic Test Interface Solutions 9Four YY Driver SharingATE Base Board DUT Socket PCB DUT Design100ohm> 100ohmL3DUT1ShortDriver50ohmCoaxial cableL1L1=L2100ohm> 100ohmL4> 100ohmL5DUT2DUT3L2> 100ohmT/L matching L6(+/- 0.1mm) L3 =L4+L5=L6Resource Share X 4DUT43/2009 Parallel Logic Test Interface Solutions 10Paper #1March 8 - 11, 20095

2009Session 3Adventures in Test & Burn-in OperationsFour Star Driver SharingATE Base Board DUT Socket PCB DUT Design> 100ohmL1DUT1> 100ohm50ohmL2DUT2DriverCoaxial cable> 100ohmL3DUT3T/L matching> 100ohm(+/- 0.1mm) L4L1=L2=L3=L4Resource Share X 4DUT43/2009 Parallel Logic Test Interface Solutions 11Four Daisy Chain Driver SharingATEBase BoardDUT Socket PCBDUTDesignL1DUT150ohm50ohmL2DUT2DriverCoaxial cableL2=L3=L4L3L4DUT3DUT4Resource Share X 43/2009 Parallel Logic Test Interface Solutions 12Paper #1March 8 - 11, 20096

2009Session 3Adventures in Test & Burn-in OperationsPPS Sharing: Fan Out w/ RelayATEDUT Socket PCBDUTPPS1RL1RL2DUT1DUT2PPS2RL3RL4DUT3DUT4Resource Share X 23/2009 Parallel Logic Test Interface Solutions 13PPS Sharing: Fan-Out w/ AmplifierFor DC testingDUT1RL1AMP(250mA)DUT2RL2DUT3RL3PPS1DUT4RL4Ext. Power supply3/2009 Parallel Logic Test Interface Solutions 14Paper #1March 8 - 11, 20097

2009Session 3Adventures in Test & Burn-in OperationsSignal Performance: Two Y Sharing137pSFreq: 400MHzVIH/VIL: 1.2v / 0.8vTR / TF: 400pSDUT Input Cap:3pFRed: Non-ShareGreen:Two-Share3/2009 Parallel Logic Test Interface Solutions 15Signal Performance: Four YY Sharing68mV250pSFreq: 400MhzVIH/VIL: 1.2v / 0.8vTR / TF : 400pSDUT Input Cap:3pFRed: Non-ShareGreen: Four-Share3/2009 Parallel Logic Test Interface Solutions 16Paper #1March 8 - 11, 20098

2009Session 3Adventures in Test & Burn-in OperationsSignal Performance: Four YY Sharing25mVFreq: 200MhzVIH / VIL: 1.2v/ 0.8vTR / TF : 800pSDUT Input Cap:3pFGreen: Non-ShareRed: Four-Share3/2009 Parallel Logic Test Interface Solutions 17DUT Socket PCBsTwo Y Driver SharePackage: 80FBGAFrequency: 250MHzFour YY Driver SharePackage: 100BOCFrequency: 400MHz3/2009 Parallel Logic Test Interface Solutions 18Paper #1March 8 - 11, 20099

2009Session 3Adventures in Test & Burn-in OperationsDUT Socket PCBsFour Daisy Chain Driver SharingPackage: 78TFBGAFrequency: 800MHz3/2009 Parallel Logic Test Interface Solutions 1932DUT Logic / SOC TestPackage: 176 eTQFPFrequency: 200MHzSocket(Inset Photo)3/2009 Parallel Logic Test Interface Solutions 20Paper #1March 8 - 11, 200910

2009Session 3Adventures in Test & Burn-in OperationsAdditional DUT Power SuppliesExternal PPS System Integrated in Logic Test InterfaceExternal Power Supplies3/2009 Parallel Logic Test Interface Solutions 21Parallel Logic / SOC Test Benefits• Reduce Cost of Test• Increased parallelism• Reduction of load board design cost• Maintenance Improvement• Individual socket boards are changeable• Individual channels to DUT are repairable• Signal Quality is Improved with Coax• Minimize cross talk• Excellent impedance control (50ohm)• Reduction of TPD3/2009 Parallel Logic Test Interface Solutions 22Paper #1March 8 - 11, 200911

2009Session 3Adventures in Test & Burn-in OperationsLogic/SOC ATE Considerations• S/W support of resource sharing modes• Calibration support of resources sharing modes• S/W support external power supply options• Force, Measure & Calibration• Test program development tools for parallel testing• ATE calibration support through interface to DUT3/2009 Parallel Logic Test Interface Solutions23High Parallel Logic Test Is Not ForEverybody….• Short test time may negate benefits of parallel test• Consider handler index time• Consider cost of handler & change kit• DUT volume may not justify higher parallelism• Consider change-over time for high mix environment• Very high I/O & mixed signal still a challenge!• Signal performance of shared I/O lines• Decreased DUT amplitude at comparator• I/O turn-around time• Am I strobing the DUT or what is in the interface?3/2009 Parallel Logic Test Interface Solutions24Paper #1March 8 - 11, 200912

2009Session 3Adventures in Test & Burn-in OperationsConclusions• Parallel Logic / SOC Test Can be Increased…. Apply parallel memory interface technology Utilize resource sharing techniques Utilize memory handlers & change kits Utilize DFT/BIST/Scan to reduce I/O requirements Pursue high speed and fine pitch applications Pursue additional DUT power supply solutions3/2009 Parallel Logic Test Interface Solutions25Paper #1March 8 - 11, 200913

2009Session 3Adventures in Test & Burn-in OperationsCID: A New BreakthroughSolution for Contactor HardwareTrackingJonathan D. Mondero – TI (Philippines)Kevin Tiernan – TI (Houston)Mike Guenther – TI (Houston)Eugene Batilo – ECT (Singapore)2009 BiTS WorkshopMarch 8 - 11, 2009Presentation TopicsBackgroundObjective / PurposeCase for Action – The Current processContactor Recording – How is it done today?The Solution: CID – ContactorCID Module – Design Architecture / DetailsTester Hardware HookupsMethodology – CID Process OverviewResults / Conclusions3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 2Paper #2March 8 - 11, 20091

2009Session 3Adventures in Test & Burn-in OperationsBackground Contactor tracking is important for better inventorymanagement and control – for better planning andcost reduction Accurate usage records are needed for proactivescheduling of maintenance To date, TI had used barcodes to manually trackcontactors and no accurate usage records exist toassociate each contactors on how often it is used3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 3Objective / Purpose We developed a new method of tracking contactorsusing an EEPROM imbedded on the contactor toprovide… Accurate Usage Records Unit-Level Data Association Real Time Monitor (RTM)3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 4Paper #2March 8 - 11, 20092

2009Session 3Adventures in Test & Burn-in OperationsCase for Action – Current ProcessCurrent practices uses stickerbarcodes that are notpermanent – They losevaluable information (history,insertion, setup issues).The barcode peel off andfade when run underextreme conditions.3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 5Contactor RecordingHow is it done today?Central ShopTest FloorCentral ShopShop Monitor Floor Monitor Shop Monitor3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 6Paper #2March 8 - 11, 20093

2009Session 3Adventures in Test & Burn-in OperationsContactor RecordingHow is it done today?Central Shop Bring up loadboard screen and scanin loadboard ID Scan in contactor(s) ID associatedwith loadboard before checking outShop Monitor3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 7Contactor RecordingHow is it done today?Test Floor Scan loadboard ID into SMSbefore running the lot Changing contactor(s) requiresscanning out old contactor andscanning new contactorFloor Monitor Re-scan loadboard before lotbegins.Very Manual Process!3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 8Paper #2March 8 - 11, 20094

2009Session 3Adventures in Test & Burn-in OperationsContactor RecordingHow is it done today?Central Shop Scan loadboard after returning fromthe tester Scan out contactor(s) beforereturning the loadboard and contactorfor storage.Shop Monitor3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 9The Solution: CID – ContactorContactor IDWorkpressEEPROMContactor AssemblyCID Base ModuleChip Cap and Resistors willbe mounted and routed to theloadboard design.3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 10Paper #2March 8 - 11, 20095

2009Session 3Adventures in Test & Burn-in OperationsCID Module – Design ArchitectureEEPROMWorkpressCID Base ModuleTwo guide pins are used tohelp register alignment tothe contactor body3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 11CID Module – Design ArchitectureThe CID module consists oftwo piece PEI (Polyetherimide)blocks and with a pin retainerplate that hold the 8 pogo pinsthat contact with DIB & IC3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 12Paper #2March 8 - 11, 20096

2009Session 3Adventures in Test & Burn-in OperationsCAT24C04WI – EEPROM Details3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 13Tester Hardware Hookups3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 14Paper #2March 8 - 11, 20097

2009Session 3Adventures in Test & Burn-in OperationsCID Process OverviewYield, CRES, CONT,Usage, PerformanceAnalysis, etc.Load BoardContactorsTestWare DBKEYTablesProduct/Test Engr.Shared MemoryContactor Management/Tracking,spares, insertion modeling,maintenance, repair, etc.IC TESTERC-Shop DBRTM (Real Time Monitor) ToolsCID, Site-to-Site, Yield, etc.3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 15CID Insertion Modeling - Results• Could lead to High Re-screen/Mistest• Can affect measurements that will lead to intermittent or false failuresThe CID will accurately model this data and provide efficiency onour preventive maintenance scheduling3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 16Paper #2March 8 - 11, 20098

2009Session 3Adventures in Test & Burn-in OperationsConclusion The CID is an intelligent and cost effective solution toimprove the way we track contactors automatically The CID addresses the need for accurate usagerecords by associating “Unit Level” data with thecontactor being used The CID can be implemented at TI without the needfor high investment or new system infrastructure The CID had been proven to work on DSPS devices3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 17Business Impact COST Better Management of Spares and Peripheral Align Capacity planning = Reduce Capital Expenditures CYCLE TIME Accurate Preventive Maintenance Scheduling = ReduceDowntime More output = On Time Delivery (OTD) YIELD IMPROVEMENTS EFFICIENCY3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 18Paper #2March 8 - 11, 20099

2009Session 3Adventures in Test & Burn-in OperationsAcknowledgements• Nick DeJesu – TI Software Development Manager• Glenn Lorig – TI DSP Systems PE Manager• Gary Dirige – TIPI Product Engineering Manager3/2009 CID: A New Breakthrough Solution for Contactor Hardware Tracking 19Paper #2March 8 - 11, 200910

2009Session 3Adventures in Test & Burn-in OperationsMechanical Reliability Testas Part of Final Test of aPackaged ChipC-Y Li, T Wooden, SM Low, TM KorhonenChe-Yu Li and Co, Ithaca, NYProtos Electronics, Santa Clara, CAADE Technologies, Singapore2009 BiTS WorkshopMarch 8 - 11, 2009Background• Final test of packaged chip typically includeselectrical and burn-in test emphasizing electricalperformance• Mechanical reliability test is typically not done• Mechanical test would identify manufacturing anddesign defects that can cause early mechanicalfailures in service• Omitting mechanical testing can become costly ifdefective chips are shipped to customer3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 2Paper #3March 8 - 11, 20091

2009Session 3Adventures in Test & Burn-in OperationsMechanical Reliability Test• Luu Nguyen’s team at NSC have shownthat power cycle test can be used and is 10xfaster compared to thermal cycling test• Integrated as a part of test socket,• Stand-alone power cycle system, with manysamples at a time3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 3Power Cycle vs. Thermal Cycle• Accelerated Temperature Cycling (ATC)– Most widely used accelerated life test– Sample is placed inside test chamber and chamber iscycled between extreme temperatures– Time consuming because of the time the chamber needsto reach test temperature• Power cycling test– Heat is generated by powered electronic device– More representative of field conditions, becausepackage is heated differentially– Typical cycle is faster than in thermal cycling3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 4Paper #3March 8 - 11, 20092

2009Session 3Adventures in Test & Burn-in OperationsPrevious Research• 2005 ECTC paper “Powercycling Reliability, Failure Analysis andAcceleration Factors of Pb-free Solder Joints” by K. Setty, G.Subbarayan and Luu Nguyen• Sample: 36 I/O WLCSP package with Pb-free Sn4Ag0.5Cu solderjoint• Test: Power cycle 0-100 °C and Temperature cycle -40-125 °C,followed by failure analysis including destructive SEM analysis• Test Results:– Power cycle: cycle time 10 min, failed after 2368 cycles– Temperature cycle: cycle time 60 min, failed after 1368 cycles– Failure mechanism similar in both samples3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 5Power Cycle Test Set-Up3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 6Paper #3March 8 - 11, 20093

2009Session 3Adventures in Test & Burn-in OperationsPower Cycle Test Details• Heating plate was made from 90 mil thick copper plate.Grooves were cut in the copper plate in which nichrome 60resistance wire was inserted. The heating element was drivenby HB-25 motor controller with PWM frequency of 9.2khz and aload current limit of 25 amps.• 42 watt Thermoelectric/Peltier Module was placed next toheating plate. The device was used in the heating cycle to heatthe device on one side with the added advantage of cooling theheat pipe and the upper aluminum support on the other side. Byreversing the power to the Peltier module we were able toshorten the heating and cooling times.• The heat pipe was placed on top of the Peltier module. Toquickly remove the heat, the other end of the heat pipe was putin an enclosure with a fan.3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 7Power Cycle Test Details (cont.)• Three thermistors were used to monitor the procedure: one onthe device to be tested, one on the heat pipe next to the heater,and the last on the heat pipe inside the fan enclosure.Temperatures were taken every 1000ms.• The system was controlled and monitored by a Parallax BasicStamp board and processor. The processor ran full power tothe heat plate up to 95 degrees C and then the programadjusted current and timing to maintain 100 degrees C. Afterthe prescribed time holding the temperature at 100 degrees C,the program turned the heat plate off, the fan on, and thereversed voltage to the Peltier module for cooling. Afterreaching 0 degrees C the cycle repeats.3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 8Paper #3March 8 - 11, 20094

2009Session 3Adventures in Test & Burn-in OperationsDevice Temperature3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 9Test Socket Requirements• Test socket with integrated power cyclingunit• Monitor changes in resistance duringmechanical testing• Low noise is essential to capture changes inresistance due to crack growth• Most test sockets do not have good enoughelectrical performance3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 10Paper #3March 8 - 11, 20095

2009Session 3Adventures in Test & Burn-in OperationsTest Socket Requirements• Low & stable resistance of electrical contact– Failure monitoring– High service temperature– High power, high current• Other requirements– High frequency– Large array– Fine contact pitch3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 11Braided Electrical ContactElement BeCe TM• Meets requirements• Multiple helical springs operating in parallelBeCe SEM Image of Tip as Cut BeCe SEM Image of Tip Plated3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 12Paper #3March 8 - 11, 20096

2009Session 3Adventures in Test & Burn-in OperationsAttributes of BeCe TM• Low Contact Force -- Large Array• High Compliance -- Low Inductance / HighFrequency• Low Resistance -- High Power• Small OD -- Fine Contact Pitch• Plated Stainless Steel Wire -- High ServiceTemperature• Multiple Contact Tips -- Redundancy• Medical Grade Braiding Wire -- Durability3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 13Single Pin Test Data18X40 BeCe Copper AlloyBeCe ( Copper alloy)•Low Force

2009Session 3Adventures in Test & Burn-in OperationsHigh Frequency Data1.0 mm pitch,5x5 array 40 mil height0.3 mm pitch,5x5 array 40 mil height3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 15BGA Interposer3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 16Paper #3March 8 - 11, 20098

2009Session 3Adventures in Test & Burn-in OperationsBeCe Data for BGA Interposer• 1 mm or 0.8 mm pitch• 1.5 on 8 copper alloy BeCe• 80 mil BeCe height• 14 mil OD• Resistance 7 mΩ• Inductance 0.6 nH• Compliance 20%• Array to 5000 I/O3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 17LGA Interposer• 0.3mm pitch• 400 I/O• 60 mil high, 6 mil OD• Inductance 0.6 NH• Resistance 20 mΩ• Contact Force

2009Session 3Adventures in Test & Burn-in OperationsProposed Usage• Integrated test socket for final test andmechanical reliability test Power cyclefor 5 days ATE• Multiple cell stand-alone system for burnintest and mechanical reliability test Periodically to test socket and ATE3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 19Conclusions• Time Effective Power Cycle SystemPossible• BeCe contact element meets requirements:– Low and stable resistance– High service temperature– High current– High frequency– Large array– Fine contact pitch3/2009 Mechanical Reliability Test as Part of Final Test of a Packaged Chip 20Paper #3March 8 - 11, 200910

2009Session 3Adventures in Test & Burn-in OperationsSubstrate Bias:Application in Final Test andBurn-in of High-Power CPU’sMax ParanskyTexas Instruments2009 BiTS WorkshopMarch 8 - 11, 2009High-Power Burn-inConditions determined by process technologyand reliability requirements:• Chip area coverage> Exercise all key structures (logic, memory, IO’s)• Time duration• Voltage levels> All transistors types powered above their normaluse conditions• Temperature> Silicon Tj above use conditions3/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 2Paper #4March 8 - 11, 20091

2009Session 3Adventures in Test & Burn-in OperationsBurn-in OvenBurn-in ovens, boards and sockets haveconstraints:• Thermal budget> Finite cooling capability per DUT• Power budget> Only so many power supplies and amps per boardProblem!These constraints limit how many units can beloaded at a time3/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 3How to Increase Throughput?• Reduce DUT power by lowering Vdd, Temp orboth> Possible with extended duration (and lots ofreliability modeling)> Usually economically impractical• Apply transistor substrate bias> Reduce DUT power without changes to Vdd andtemperature setpointsWhat’s substrate bias?3/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 4Paper #4March 8 - 11, 20092

2009Session 3Adventures in Test & Burn-in OperationsTransistor Substrate BiasVsb Vss GG Vdd VnwGNDNNP-substratePPN-wellVdd3-terminal device: no substrate bias, Vsb = Vss, Vnw = VddVsbVssGGVddVnwGNDNNP-substratePPN-wellVdd4-terminal device: biased substrate, Vsb ≠ Vss, Vnw ≠ Vdd3/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 5Reverse Bias Mechanism• Increased potential across thetransistor> More V needed to create inversionlayer in channel, so Vt increases• Idsat α (Vgs – Vt)Vss> With fixed Vgs (Vdd) there is now less charge to carrychannel current Idsat> As Vt increases, Idsat decreases, and therefore totalDUT power decreasesSGVsbD3/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 6Paper #4March 8 - 11, 20093

2009Session 3Adventures in Test & Burn-in OperationsBurn-in DataAverage 38% of power saved by reverse substrate bias> Unit-to-unit savings range is 23% - 58%Vnw = Vdd + 0.5VVsb = - 0.5VEffect of Vnw and Vsb bias on core IddCore Idd% powersaved100.080.060.040.020.0units0.03/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 7• Vnw is positiveOven Complications> But occupies oven power supplies that could otherwisebe used for core Vdd• Vsb is negative> Oven doesn’t have a negative power supply> A custom board-level circuit was added for +DC/-DCconversion• Adjust thermal control to avoid under-temps forlow-power samples> Tune oven heat/cool rate of response> Tune oven ambient temperature3/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 8Paper #4March 8 - 11, 20094

2009Session 3Adventures in Test & Burn-in OperationsDevice LimitationsIncreased gate-substrate potentialhas negative effects:• Wider channel> Gate-drain leakage increase• Higher drain-substratejunction potential> Drain-substrate leakageincrease• Optimal range of substratebias> Beyond that combined leakageoverwhelms any Idd savings andtotal current actually increasesTotalCurrentCore IddLeakageSP-substrateGOptimalrangeDVsbVsb/Vnw3/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 9Burn-in ThroughputPower savings with substrate bias are projected to:• Reduce fallout due to BI power by 66%> Good units previously beyond oven cooling capacity• Increase weekly BI throughput by 75%> Optimized DUT per board loading3/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 10Paper #4March 8 - 11, 20095

2009Session 3Adventures in Test & Burn-in OperationsTest and System• ATE> High speed / high power testing pushes coolingcapability of handlers• End system> High speed / high power real applications push systemcooling capabilities3/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 11Mechanism Revisited• Idsat α (Vgs – Vt)> Fixed Vgs (Vdd) and adjustable Vt:a) Modulate Idsat and total DUT powerb) Modulate switching time and overall chipperformance (max frequency)3/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 12Paper #4March 8 - 11, 20096

2009Session 3Adventures in Test & Burn-in OperationsFrequency ApplicationsDUTs too slowApply forwardbias to speedupVnw < VddVsb > VssDesiredDistributionActualDistributionDUTs too high-powerApply reversebias forcoolingVnw > VddVsb < VssDUT frequency3/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 13Tester Frequency DataOn average 4% of DUT frequency gained by forwardsubstrate biasVnw = Vdd - 0.3VVsb = 0.3V12.0%10.0%8.0%6.0%4.0%2.0%0.0%-2.0%Forward Substrate BiasFrequency GainDUTs3/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 14Paper #4March 8 - 11, 20097

2009Session 3Adventures in Test & Burn-in OperationsConclusionModulating substrate bias allows:• Increased BI yield due to power/cooling fallout• Optimized BI oven/board resource use• Increased max frequency on slow devices in test/system• Cooling for fast/leaky devices in test/systemThank You!3/2009 Substrate Bias: Application in Final Test and Burn-in of High-Power CPU’s 15Paper #4March 8 - 11, 20098