ARCHIVE 2009 - BiTS Workshop

2009Session 3Adventures in Test & Burn-in OperationsConclusions• Parallel Logic / SOC Test Can be Increased…. Apply parallel memory interface technology Utilize resource sharing techniques Utilize memory handlers & change kits Utilize DFT/BIST/Scan to reduce I/O requirements Pursue high speed and fine pitch applications Pursue additional DUT power supply solutions3/2009 Parallel Logic Test Interface Solutions25Paper #1March 8 - 11, 200913