ARCHIVE 2009 - BiTS Workshop

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2009Session 3Adventures in Test & Burn-in OperationsOne-Piece PCB Logic Load Board• Planarity & contact issues• Poor thermal performance• Limited real estate for additional circuitryTest SocketsLoad Board• PCB size limitations for high parallelism• PCB aspect ratio limitations for fine pitch applications• Costly PCB design & layout costs for high density &high speed performance• PCB yield & cost issues for high density & performance• Very limited repair & maintenance options3/2009 Parallel Logic Test Interface Solutions5New Test Interface Technology• Extensive real estate for additional circuitry• Excellent tri-temp thermal performance• Excellent planarity & contact16 DUT800MHz• Excellent impedance control• Small PCB size• Enables high parallelism• Reduces PCB yield loss• Improves aspect ratio for fine pitch applications• Modular structure provides repair options3/2009 Parallel Logic Test Interface Solutions6Paper #1March 8 - 11, 20093
2009Session 3Adventures in Test & Burn-in OperationsStructure of New Logic Test InterfaceIndividual Test SocketsIndividual Sockets PCBsSpring Towersfor Isolationand FloatCoax InterconnectSystem InsideProtective HousingConnectorsfor TH Connection3/2009 Parallel Logic Test Interface Solutions7Structure of New Logic Test InterfaceTest SocketSocket PCBVertical PCBCable or ConnectorTerminationRealEstateCloseTo DUTBothSides!!3/2009 Parallel Logic Test Interface Solutions8Paper #1March 8 - 11, 20094
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ARCHIVE 2009 - BiTS Workshop

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