System Architecture Design

pSHIELDSystem Architecture DesignPUthe ES design with SPD features. For example, the memory can be realized by ROM, RAM, and FLASH,the radio can be 802.15.4, 802.11, RFID, UWB, etc. and the interfaces can be ADC and DAC, Timer,UART, I2C, etc. Finally, the multi-core processor can be realized as single microcontroller for nano andmicro nodes or more than one core microcontroller for personal nodes and multi-core processor for powernode (SPD & HSM, Application and Specific processors).Today 3D integration nano-technology offers a new perspective for extremely complex heterogeneousSystem On Chip (SoC) design. The following figure shows hardware architecture of SoC design.Figure 18 - Hardware architecture and nano node chip partitioning.To address the innovative issues and challenges in pSHIELD, solutions and long-term objectives areproposed for the development of pSHIELD Nano Nodes:• A new hardware architecture described in above figure is proposed based on two Innovative SPDcomponents:− an intelligent low power smart sensor with on chip detection capability− a digital image processing and communication chip based on optimized signal processor• Low power nano node with a target of less than 1mW by defining and implementing a multi-levelpower management strategy• Miniaturization through 3D Integration with special care for thermal study and electricalinteractions between analogue, digital and RF• Autonomous system working on a battery and communicating an optimized dataflow throughwireless RF linkFor a typical multi-task software application running on a mono-processor architecture (MIPS32 processorcore with separated data and instruction caches), the ultra-low power processor chip can be designed byPUD2.3.2Issue 5 Page 79 of 122