Xilinx Partial Reconfiguration User Guide

Configuration by Means of PCIe InterfaceConfiguration by Means of PCIe InterfacePartial Reconfiguration can create a new configuration port utilizing an interface standardmore compatible with the system architecture. For example, the FPGA device could be aperipheral on a PCIe bus and the system host could configure the FPGA through the PCIeconnection. After power-on reset the FPGA device must be configured with a full bit file.However, the full bit file might only contain the PCIe interface and connection to theInternal Configuration Access Port (ICAP).Bitstream compression can be used to reduce the size and therefore configuration time ofthis initial device load, helping the FPGA configuration meet PCIe enumerationspecifications.The system host could then configure the majority of the FPGA functionality with a partialbit file downloaded through the PCIe port as shown in Figure 2-3.X-Ref Target - Figure 2-3ICAPFullBit FilePCIeStaticPartialBit FileX12021Figure 2-3:Configuration by Means of PCIe InterfaceThe PCIe standard requires the peripheral (the FPGA device in this case) to acknowledgeany requests even if it cannot service the request. Reconfiguring the entire FPGA devicewould violate this requirement. Because the PCIe interface is part of the static logic, it isalways active during the Partial Reconfiguration process thus ensuring that the FPGAdevice can respond to PCIe commands even during reconfiguration. This use case isextensively documented in Fast Configuration of PCI Express Technology through PartialReconfiguration (XAPP883). A reference design that targets the ML605 evaluation board isincluded with the Application Note.Partial Reconfiguration User Guide www.xilinx.com 17UG702 (v13.1) March 1, 2011