Xilinx Partial Reconfiguration User Guide

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Chapter 3: Software Tools Flowred_slowblue_fastblue_slowgreen_fastgreen_slowImplementation . . . . implementation results from scripted runsFastConfig. . . . . contains implementation results and bit filesSlowConfig. . . . . ""FSFConfig . . . . . ""BlankConfig . . . . contains black boxes for the three colorsPlanAhead. . . . . . . implementation results from PlanAhead runsFFF . . . . . . . . contains implementation results and bit filesSSS . . . . . . . . ""FSF . . . . . . . . ""BB. . . . . . . . . contains black boxes for the three colorsTools. . . . . . . . . Tcl scripts or any other user scriptsSynthesisEach Reconfigurable Module is synthesized independently from the others in a bottom-upfashion. This can be done through the use of independent projects, either through agraphical interface or on the command line. For each module, be sure to disable I/Oinsertion, as the ports of these modules (in most cases) do not connect to package pins, butto the static logic above it. I/O ports may be included to be reconfigured. For moreinformation, see I/O in Reconfigurable Modules in Chapter 7.The static modules can be synthesized together to generate one netlist or individually togenerate multiple static netlists. The NGDBuild utility merges the static and reconfigurablemodules, and the Reconfigurable Partition definitions denote the interfaces between thestatic and reconfigurable logic. Different options can be used for any of the static orreconfigurable module synthesis.The minimum generated netlists for the example design, Color2, are shown in thefollowing code snippet:Netlists generated for the PR project named Color2:Netlist for Top which contains DVI_IF, IIC_init and VGA modulesNetlists for the reconfigurable instance Red:--------------Netlist for red_fastNetlist for red_slowNetlists for the reconfigurable instance Blue:--------------Netlist for blue_fastNetlist for blue_slowNetlists for the reconfigurable instance Green:--------------Netlist for green_fastNetlist for green_slowCaution! The netlist names are related to the module name, not the HDL file name. Themodule/netlist name for each Red must be identical to allow the instantiation of the module in thestatic logic to call any of the Reconfigurable Modules. In addition, the ports of eachReconfigurable Module must be identical so the assembly of the design can succeed.24 www.xilinx.com Partial Reconfiguration User GuideUG702 (v13.1) March 1, 2011
ConfigurationsEach instantiation of a reconfigurable module must have a unique module name. In thissample design, Red can be instantiated only once. This allows the implementation tools todetermine which Reconfigurable Modules are associated with which ReconfigurablePartition.In practice, the netlist name of each Reconfigurable Module is identical, requiring that eachnetlist be in its own directory:Netlist directory for the PR project named Color2:Static/Top.ngc (contains logic for all static logic includingDVI_IF, IIC_init and VGA)Netlists for the reconfigurable instance Red:--------------red_fast/red.ngcred_slow/red.ngcNetlists for the reconfigurable instance Blue:--------------blue_fast/blue.ngcblue_slow/blue.ngcNetlists for the reconfigurable instance Green:--------------green_fast/green.ngcgreen_slow/green.ngcConfigurationsThe Partial Reconfiguration software implements a full design containing static logic andone Reconfigurable Module for each Reconfigurable Partition. Each implementation isdone in context. This gives the tools a complete set of information for resource usage,global signals, design constraints, and other requirements. To implement allReconfigurable Modules, you must choose a subset of all possible Reconfigurable Modulecombinations and implement them as unique designs. Each unique implementation iscalled a Configuration.Each Reconfigurable Partition can be optionally set as a black box, leaving a “blanking”bitstream as a Reconfigurable Module. Therefore, in the Color2 design the full set ofReconfigurable Modules, and therefore partial BIT files, that can be implemented are:Red { red_fast, red_slow, black box }Blue { blue_fast, blue_slow, black box }Green { green_fast, green_slow, black box }With three choices for each Reconfigurable Partition, and three RPs in this design, there are27 unique combinations that can define a Configuration. However, it is not necessary tocreate a Configuration for each combination. It is sufficient to implement only theConfigurations that contain each module once, since the partial bit file for a module isindependent of the other Reconfigurable Modules.Partial Reconfiguration User Guide www.xilinx.com 25UG702 (v13.1) March 1, 2011
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Page 6 and 7: Chapter :Chapter 5: Command Line Sc
Page 8 and 9: Chapter 1: IntroductionTerminologyA
Page 10 and 11: Chapter 1: IntroductionStatic Logic
Page 12 and 13: Chapter 1: Introduction• While Vi
Page 14 and 15: Chapter 2: Common ApplicationsThis
Page 16 and 17: Chapter 2: Common ApplicationsDynam
Page 18: Chapter 2: Common ApplicationsX-Ref
Page 21: Example Project File StructureRed,
Page 25 and 26: ConstraintsAt least one and possibl
Page 27 and 28: ConstraintsPartition PinsHowever, t
Page 29 and 30: ConstraintsThe PIN-TPSYNC grouping
Page 31 and 32: ConstraintsExtracting Partition Pin
Page 33 and 34: Partitions and ImportPartitions and
Page 35 and 36: Partitions and ImportSecond Configu
Page 37 and 38: ImplementationDebugging Placement a
Page 39 and 40: Report FilesThe following BitGen op
Page 41 and 42: Report FilesIn the following exampl
Page 43 and 44: Report FilesThe timing report can b
Page 45 and 46: Report FilesFigure 3-8 illustrates
Page 47 and 48: Report FilesX-Ref Target - Figure 3
Page 49 and 50: pr_verifypr_verify Log FileThe samp
Page 51 and 52: Flow DifferencesFlow DifferencesThe
Page 53 and 54: Chapter 4PlanAhead SupportThis chap
Page 55 and 56: Setting the Project as a PR Project
Page 57 and 58: Defining the Reconfigurable Instanc
Page 59 and 60: Adding Reconfigurable Modules to th
Page 65 and 66: Running Partial Reconfiguration Des
Page 67 and 68: Creating ConfigurationsX-Ref Target
Page 69 and 70: Controlling ConfigurationsControlli
Page 71 and 72: Controlling ConfigurationsX-Ref Tar
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Controlling ConfigurationsBecause R
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Generating BIT FilesGenerating BIT
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Chapter 5Command Line ScriptingTcl
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Data.tcl Format# 2:part definitionD
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Data.tcl Format# Configuration FSFC
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Recommended FlowRecommended Flow•
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Required Files and Directory Struct
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Chapter 6Configuring the FPGA Devic
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Downloading a Partial Bit FileDownl
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Partial Bit File IntegrityPartial B
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Configuration FramesX-Ref Target -
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Configuration DebuggingXilinx ASCII
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Configuration Debugging• Icap_o_t
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Chapter 7Design ConsiderationsDesig
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Design Hierarchy//XST Verilog examp
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Design HierarchyPacking Input/Outpu
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Clocking RulesRegional ClockingThe
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Design Revision ChecksDesign Revisi
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Module-Level Constraint FilesEven t
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Interaction with Other Xilinx Tools
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Partial Reconfiguration Design Chec
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Appendix AKnown Issues and Known Li
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Appendix BPartial Reconfiguration M
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Migrating a DesignBUFRs Require Par
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Migrating a DesignExample - New VHD
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Appendix CAdditional ResourcesTo fi
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