Xilinx Partial Reconfiguration User Guide

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Partial Reconfiguration User Guide www.xilinx.com UG702 (v13.1) March 1, 2011
Table of ContentsRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Chapter 1: IntroductionPartial Reconfiguration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Partial Reconfiguration Design Criteria for ISE 13.1. . . . . . . . . . . . . . . . . . . . . . . . . . 12Chapter 2: Common ApplicationsNetworked Multiport Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Configuration by Means of PCIe Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Dynamically Reconfigurable Packet Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Asymmetric Key Encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Chapter 3: Software Tools FlowExample Design Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Example Project File Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Partitions and Import . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Generating BIT Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Report Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40pr_verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Flow Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Chapter 4: PlanAhead SupportCreating a Partial Reconfiguration Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Setting the Project as a PR Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Opening the Netlist Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Defining the Reconfigurable Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Adding Reconfigurable Modules to the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Running Partial Reconfiguration Design Rule Checks . . . . . . . . . . . . . . . . . . . . . . . 65Creating Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Controlling Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Verifying Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Generating BIT Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75PlanAhead Project Directory Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Partial Reconfiguration User Guide www.xilinx.com 5UG702 (v13.1) March 1, 2011
Page 1 and 2: PartialReconfigurationUser Guide[Gu
Page 6 and 7: Chapter :Chapter 5: Command Line Sc
Page 8 and 9: Chapter 1: IntroductionTerminologyA
Page 10 and 11: Chapter 1: IntroductionStatic Logic
Page 12 and 13: Chapter 1: Introduction• While Vi
Page 14 and 15: Chapter 2: Common ApplicationsThis
Page 16 and 17: Chapter 2: Common ApplicationsDynam
Page 18: Chapter 2: Common ApplicationsX-Ref
Page 21 and 22: Example Project File StructureRed,
Page 23 and 24: ConfigurationsEach instantiation of
Page 25 and 26: ConstraintsAt least one and possibl
Page 27 and 28: ConstraintsPartition PinsHowever, t
Page 29 and 30: ConstraintsThe PIN-TPSYNC grouping
Page 31 and 32: ConstraintsExtracting Partition Pin
Page 33 and 34: Partitions and ImportPartitions and
Page 35 and 36: Partitions and ImportSecond Configu
Page 37 and 38: ImplementationDebugging Placement a
Page 39 and 40: Report FilesThe following BitGen op
Page 41 and 42: Report FilesIn the following exampl
Page 43 and 44: Report FilesThe timing report can b
Page 45 and 46: Report FilesFigure 3-8 illustrates
Page 47 and 48: Report FilesX-Ref Target - Figure 3
Page 49 and 50: pr_verifypr_verify Log FileThe samp
Page 51 and 52: Flow DifferencesFlow DifferencesThe
Page 53 and 54:
Chapter 4PlanAhead SupportThis chap
Page 55 and 56:
Setting the Project as a PR Project
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Defining the Reconfigurable Instanc
Page 59 and 60:
Adding Reconfigurable Modules to th
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Page 63 and 64:
Page 65 and 66:
Running Partial Reconfiguration Des
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Creating ConfigurationsX-Ref Target
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Controlling ConfigurationsControlli
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Controlling ConfigurationsX-Ref Tar
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Controlling ConfigurationsBecause R
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Generating BIT FilesGenerating BIT
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Chapter 5Command Line ScriptingTcl
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Data.tcl Format# 2:part definitionD
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Data.tcl Format# Configuration FSFC
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Recommended FlowRecommended Flow•
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Required Files and Directory Struct
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Chapter 6Configuring the FPGA Devic
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Downloading a Partial Bit FileDownl
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Partial Bit File IntegrityPartial B
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Configuration FramesX-Ref Target -
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Configuration DebuggingXilinx ASCII
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Configuration Debugging• Icap_o_t
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Chapter 7Design ConsiderationsDesig
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Design Hierarchy//XST Verilog examp
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Design HierarchyPacking Input/Outpu
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Clocking RulesRegional ClockingThe
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Design Revision ChecksDesign Revisi
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Module-Level Constraint FilesEven t
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Interaction with Other Xilinx Tools
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Partial Reconfiguration Design Chec
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Appendix AKnown Issues and Known Li
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Appendix BPartial Reconfiguration M
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Migrating a DesignBUFRs Require Par
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Migrating a DesignExample - New VHD
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Appendix CAdditional ResourcesTo fi
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Xilinx Partial Reconfiguration User Guide

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