Xilinx Partial Reconfiguration User Guide

Chapter 1IntroductionPartial Reconfiguration is the modification of an operating FPGA design by loading apartial configuration file. This guide describes how to create and implement an FPGAdesign that is partially reconfigurable using a modular design technique calledPartitioning. Module instances in the design are translated into partial BIT files whichdefine the new hardware function. Other techniques such as the differencing methoddescribed in the Application Note: Differencing Method for Partial Reconfiguration(XAPP290) are not covered in this guide. For supplemental material, see Appendix C,Additional Resources.This guide:• Is intended for designers who want to create a Partially Reconfigurable FPGA design• Assumes familiarity with FPGA design software, particularly Xilinx ® ISE ® DesignSuite and the PlanAhead software.• Has been written specifically for ISE Design Suite Release 13.1. This release supportsPartial Reconfiguration for Virtex ® -4, Virtex-5, and Virtex-6 devices only.Partial Reconfiguration OverviewFPGA technology provides the flexibility of on-site programming and re-programmingwithout going through re-fabrication with a modified design. Partial Reconfiguration (PR)takes this flexibility one step further, allowing the modification of an operating FPGAdesign by loading a partial configuration file, usually a partial bit file. After a full bit fileconfigures the FPGA, partial BIT files can be downloaded to modify reconfigurable regionsin the FPGA without compromising the integrity of the applications running on thoseparts of the device that are not being reconfigured.Figure 1-1 illustrates the premise behind Partial Reconfiguration.X-Ref Target - Figure 1-1FPGAReconfigBlock “A”A4.bitA3.bitA2.bitA1.bitX12001Figure 1-1:Basic Premise of Partial ReconfigurationPartial Reconfiguration User Guide www.xilinx.com 9UG702 (v13.1) March 1, 2011