Xilinx Partial Reconfiguration User Guide

Chapter 3: Software Tools FlowX-Ref Target - Figure 3-7Path AnalyzedPartition pinred. addr(11)red(partition)FFLUTaddr(11)_PROXYFigure 3-7:count_34Path from static FF to Partition PinFor the following example, a TPSYNC constraint was applied to the red.d_out bus withthese constraints:PIN "red.d_out(*)" TPSYNC = "Bram_output_PPs";TIMESPEC TS_from_PP_output_to_static = FROM "Bram_output_PPs" 5.0 ns;The source of this path is the proxy logic on the output of a Reconfigurable Partition. Thedestination is a PAD in the static region. The source name for this specific path isred.d_out(5), indicating the Partition name is red and the port name is d_out(5).The following analysis shows that the propagation time through the proxy logic is takeninto consideration, along with the net delay to the output buffer, followed by thepropagation delay through the output buffer to the PAD.Timing constraint: TS_from_PP_output_to_static = MAXDELAY FROM TIMEGRP"Bram_output_PPs" 5.0 ns;8 paths analyzed, 8 endpoints analyzed, 0 failing endpoints0 timing errors detected. (0 setup errors, 0 hold errors)Maximum delay is 4.770ns.----------------------------------------------------------------------Slack:0.230ns (requirement - data path)Source:red/d_out(5)_PROXY (LUT) (red.d_out(5))Destination: out_bram[5] (PAD)Requirement: 5.000nsData Path Delay: 4.770ns (Levels of Logic = 2)Maximum Data Path: U1_RP_Bram/d_out(5)_PROXY to out_bram[5]Location Delay type Delay(ns) Physical ResourceLogical Resource(s)(Partition Pin)-------------------------------------------- -------------------SLICE_X33Y38.B Tilo 0.080 red/d_out(5)_PROXYred/d_out(5)_PROXY(red.d_out(5))G15.O net (fanout=1) 2.514 out_bram_5_OBUFG15.PAD Tioop 2.176 out_bram[5]out_bram_5_OBUFout_bram[5]-------------------------------------------- ---------------------Total4.770ns (2.256ns logic, 2.514ns rte)(47.3% logic, 52.7% route)X1202846 www.xilinx.com Partial Reconfiguration User GuideUG702 (v13.1) March 1, 2011