Xilinx Partial Reconfiguration User Guide

Chapter 3: Software Tools FlowExample Design StructureThe top gray box represents the synthesis of HDL source to netlists for each module. Theappropriate netlists are implemented in each design to generate the full and partial BITfiles for that configuration. The static logic from the first implementation is shared amongall subsequent design implementations.Throughout this guide, the Color2 sample design is used to illustrate design flow andtechniques. This design displays on a DVI support monitor color bars of primary color red,blue, and non-primary green as well as the different shades of mixing the primary colors.The partial Reconfigurable Modules are the red, blue and green modules. The variants ofeach of the modules are fast and slow for each red, blue and green. The speed of the colorrepresents how fast the LEDs are blinking on the demo board – this design targets theVirtex ® -6 ML-605 Evaluation Platform.Design files for the referenced design can be downloaded from:http://www.xilinx.com/tools/partial-reconfigurationFigure 3-2 is a diagram of the hierarchical netlist. Top, IIC_init, DVI_IF, and VGA aremodules in the static region of the design, meaning this logic maintains normal operationwhile the other modules can be reconfigured. red, blue, and green are the instantiations ofReconfigurable Module for the Red, Blue, and Green functionality. The modules that areinterchanged are the fast and slow variants for each color module.X-Ref Target - Figure 3-2TOPDVI_IF ICC_init VGA Red Blue GreenStatic ModulesFigure 3-2:Reconfigurable PartitionsColor2 Design HierarchyX12025The following is a code snippet of the design source hierarchy and Reconfigurable Modulevariants for the overall PR Project named Color2:Design source hierarchy and Reconfigurable Module variants for overallPR project named Color2:Top.v . . . . . . . . . top module which is staticred. . . . . . . . . . instantiation of a Reconfigurable Modulered_fast.v. . . . . . Reconfigurable Modulered_slow.v. . . . . . ""blue . . . . . . . . . instantiation of a Reconfigurable Moduleblue_fast.v . . . . . Reconfigurable Moduleblue_slow.v . . . . . ""green. . . . . . . . . instantiation of a Reconfigurable Modulegreen_fast.v. . . . . Reconfigurable Modulegreen_slow.v. . . . . ""DVI_IF.v . . . . . . . static moduleIIC_init.v . . . . . . ""VGA.v. . . . . . . . . ""22 www.xilinx.com Partial Reconfiguration User GuideUG702 (v13.1) March 1, 2011