Xilinx Partial Reconfiguration User Guide

Chapter 3: Software Tools FlowTiming constraint: TS_static_VGA_vgaclk2_i = PERIOD TIMEGRP“static_VGA_vgaclk2_i” TS_static_VGA_pixel_clock_i PHASE 3.167 ns HIGH 50%;126 paths analyzed, 36 endpoints analyzed, 10 failing endpoints10 timing errors detected. (10 setup errors, 0 hold errors, 0 component switching limiterrors)Minimum period is 15.401ns.----------------------------------------------------------------------------Slack:-0.451ns (req-(data path-clock path skew + uncer'ty))Source:static_VGA/VGA_R_1[0] (FF)Destination:static_DVI_IF/ODDR_DVI_DATA11 (FF)Requirement:3.167nsData Path Delay: 3.387ns (Levels of Logic = 2)Clock Path Skew: 0.084ns (1.427 - 1.343)Source Clock:static_VGA/pixel_clock rising at 0.000nsDestination Clock: VGA_CLK rising at 3.167nsClock Uncertainty: 0.315nsClock Uncertainty:0.315ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PETotal System Jitter (TSJ): 0.070nsTotal Input Jitter (TIJ): 0.000nsDiscrete Jitter (DJ): 0.458nsPhase Error (PE):0.050nsMaximum Data Path: static_VGA/VGA_R_1[0] to static_DVI_IF/ODDR_DVI_DATA11Location Delay type Delay(ns) Physical ResourceLogical Resource(s)(Partition Pin)---------------------------------------------- -------------------SLICE_X25Y75.DQ Tcko 0.326 VGA_R_bus_out[1]static_VGA/VGA_R_1[0]SLICE_X25Y76.C6 net (fanout=8) 0.248 VGA_R_bus_out[1]SLICE_X25Y76.C Tilo 0.080 red/VGA_out7_PROXYred/VGA_in7_PROXY(red.VGA_in7)SLICE_X25Y76.D5 net (fanout=1) 0.164 red/VGA_out7SLICE_X25Y76.D Tilo 0.080 red/VGA_out7_PROXYred/VGA_out7_PROXY(red.VGA_out7)OLOGIC_X2Y39.D1 net (fanout=1) 2.192 VGA_R[7]OLOGIC_X2Y39.CLK Todck 0.297 DVI_LCD_DATA11_cstatic_DVI_IF/ODDR_DVI_DATA11---------------------------------------------- ----------------------Total3.387ns (0.783ns logic, 2.604ns rte)(23.1% logic, 76.9% rte)Figure 3-9, page 49 illustrates the path from FF to FF through partition pins.48 www.xilinx.com Partial Reconfiguration User GuideUG702 (v13.1) March 1, 2011