Xilinx Partial Reconfiguration User Guide

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Chapter 3: Software Tools FlowX-Ref Target - Figure 3-3BRAMX3Y18SLICEX42Y157SLICEX42Y156AG_PRregionABRAMX0Y0SLICEX2Y1SLICEX2Y0SLICEX3Y1SLICEX3Y0X12026Figure 3-3:Slice Range and BRAM Range for a PR RegionThe following code snippet is an AREA_GROUP RANGE constraint example with Slices andBRAM:AREA_GROUP “AG_PRregionA” RANGE = SLICE_X2Y0:SLICE_X43Y157;AREA_GROUP “AG_PRregionA” RANGE = RAMB16_X0Y0:RAMB16_X3Y18;The PlanAhead software estimates the size of each RM and displays the resources used,which is useful in determining if an AREA_GROUP RANGE is necessary for Block RAM orI/O.28 www.xilinx.com Partial Reconfiguration User GuideUG702 (v13.1) March 1, 2011
ConstraintsPartition PinsHowever, the tools cannot make recommendations as to the shape or placement of theReconfigurable Partition. The AREA_GROUP RANGE must be large enough to accommodatethe largest RM for each resource type (that is, the RM using the most Slices might not be theRM using the most BRAM), and it must be shaped and placed in a way that allows thedesign to meet timing.PR designs contain special components named Partition Pins at the port boundarybetween static logic and reconfigurable logic. Partition Pins are necessary to guarantee thatthe circuit connections between the static logic and the different RMs for each RP areidentical. The Partition Pin is also a convenient component for creating timing constraintson nets that pass to, from, or through the RP boundary.Partition Pins are inserted automatically by the implementation software. No specialinstantiations or other considerations are required of the designer, with the exception ofcontrolled routes, which is described in Chapter 7, Design Considerations.Note: Partition Pins can be input or output connections to a reconfigurable region. Partition Pinscannot be bidirectional.Partition Pin timing constraints take one of several forms depending on path structure asillustrated in Figure 3-4, page 30. The yellow RM bounding box represents the logicalboundary, not necessarily a physical range or floorplan.Path A) Static net input to a Partition PinPath B) Reconfigurable net output of a Partition PinPath C) Reconfigurable net input to a Partition PinPath D) Static net output of a Partition PinPaths X, Y and Z) Register-to-register paths that contain a PartitionPin in the pathPartial Reconfiguration User Guide www.xilinx.com 29UG702 (v13.1) March 1, 2011
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Page 6 and 7: Chapter :Chapter 5: Command Line Sc
Page 8 and 9: Chapter 1: IntroductionTerminologyA
Page 10 and 11: Chapter 1: IntroductionStatic Logic
Page 12 and 13: Chapter 1: Introduction• While Vi
Page 14 and 15: Chapter 2: Common ApplicationsThis
Page 16 and 17: Chapter 2: Common ApplicationsDynam
Page 18: Chapter 2: Common ApplicationsX-Ref
Page 21 and 22: Example Project File StructureRed,
Page 23 and 24: ConfigurationsEach instantiation of
Page 25: ConstraintsAt least one and possibl
Page 29 and 30: ConstraintsThe PIN-TPSYNC grouping
Page 31 and 32: ConstraintsExtracting Partition Pin
Page 33 and 34: Partitions and ImportPartitions and
Page 35 and 36: Partitions and ImportSecond Configu
Page 37 and 38: ImplementationDebugging Placement a
Page 39 and 40: Report FilesThe following BitGen op
Page 41 and 42: Report FilesIn the following exampl
Page 43 and 44: Report FilesThe timing report can b
Page 45 and 46: Report FilesFigure 3-8 illustrates
Page 47 and 48: Report FilesX-Ref Target - Figure 3
Page 49 and 50: pr_verifypr_verify Log FileThe samp
Page 51 and 52: Flow DifferencesFlow DifferencesThe
Page 53 and 54: Chapter 4PlanAhead SupportThis chap
Page 55 and 56: Setting the Project as a PR Project
Page 57 and 58: Defining the Reconfigurable Instanc
Page 59 and 60: Adding Reconfigurable Modules to th
Page 65 and 66: Running Partial Reconfiguration Des
Page 67 and 68: Creating ConfigurationsX-Ref Target
Page 69 and 70: Controlling ConfigurationsControlli
Page 71 and 72: Controlling ConfigurationsX-Ref Tar
Page 73 and 74: Controlling ConfigurationsBecause R
Page 75 and 76: Generating BIT FilesGenerating BIT
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Chapter 5Command Line ScriptingTcl
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Data.tcl Format# 2:part definitionD
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Data.tcl Format# Configuration FSFC
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Recommended FlowRecommended Flow•
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Required Files and Directory Struct
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Chapter 6Configuring the FPGA Devic
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Downloading a Partial Bit FileDownl
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Partial Bit File IntegrityPartial B
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Configuration FramesX-Ref Target -
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Configuration DebuggingXilinx ASCII
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Configuration Debugging• Icap_o_t
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Chapter 7Design ConsiderationsDesig
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Design Hierarchy//XST Verilog examp
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Design HierarchyPacking Input/Outpu
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Clocking RulesRegional ClockingThe
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Design Revision ChecksDesign Revisi
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Module-Level Constraint FilesEven t
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Interaction with Other Xilinx Tools
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Partial Reconfiguration Design Chec
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Appendix AKnown Issues and Known Li
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Appendix BPartial Reconfiguration M
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Migrating a DesignBUFRs Require Par
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Migrating a DesignExample - New VHD
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Appendix CAdditional ResourcesTo fi
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