Xilinx Partial Reconfiguration User Guide

Asymmetric Key EncryptionAsymmetric Key EncryptionThere are some new applications that are not possible without Partial Reconfiguration. Avery secure method for protecting the FPGA configuration file can be architected whenPartial Reconfiguration and asymmetric cryptography are combined. (See Public-keycryptography for asymmetric cryptography details.)In Figure 2-5, all of the functions in the blue box can be implemented within the physicalpackage of the FPGA. The cleartext information and the private key never leave awell-protected container.X-Ref Target - Figure 2-5Key Co-generationcleartextPublic KeyfciphertextPrivate KeyfcleartextX12022Figure 2-5:Asymmetric Key EncryptionIn a real implementation of this design, the initial bit file is an unencrypted design thatdoes not contain any proprietary information. The initial design only contains thealgorithm to generate the public-private key pair and the interface connections betweenthe host, FPGA and ICAP.After the initial bit file is loaded, the FPGA device generates the public-private key pair.The public key is sent to the host which uses it to encrypt a partial bit file. The encryptedpartial bit file is downloaded to the FPGA device where it is decrypted and sent to theICAP to partially reconfigure the FPGA device as shown in Figure 2-6, page 20.Partial Reconfiguration User Guide www.xilinx.com 19UG702 (v13.1) March 1, 2011