165-GHz Transceiver in SiGe Technology - Computer Engineering ...

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1090 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 5, MAY 2008 Fig. 7. Quadrature oscillator schematic. Odd mode: Quadrature mode: Finally, (7) describes the quadrature oscillation condition and is obtained from inequalities (3), (4), and (5) and from (6), where is the negative resistance of the active device. It should be noted that, although the roles of and are not immediately apparent from the model of Fig. 5(a), they are critical in determining the phases of the oscillator outputs in a circuit implementation. Since the order of the entries of the quadrature-mode eigenvectors of (2) can be interchanged without affecting the solution, and are responsible for establishing the exact phase relationships of the four outputs (i.e., which output is 0 , which is 90 , etc.). Furthermore, and help with suppressing the odd and even oscillation modes by significantly degrading the of the capacitor in Fig. 6(a) and (b). (4) (5) (6) (7) Fig. 8. Layout detail of the quadrature oscillator. Based on the concepts described above, the oscillator shown in Fig. 7 was designed for quadrature operation at a fundamental frequency of 80 GHz. Since AMOS varactors were not available in this technology, the oscillator was designed to operate at a constant frequency. However, more recent work in CMOS [15] illustrates that it is straightforward to extend this oscillator to a voltage-tunable version. In this design, the load resistor (of Fig. 5(a), where the fourth-harmonic signal is produced, is implemented with the bias resistors and . Cascode transistors are employed to adequately isolate the quadrature outputs from the tank. They also allow combining the two differential 80-GHz signals into two second-harmonic signals at 160 GHz that are 180 out of phase. All transistors in the oscillator are biased at the peakcurrent density of 14 mA/ m to obtain the maximum output swing. Particular attention was paid to the symmetry of the oscillator layout, both for differential and for quadrature signals, as is illustrated in Fig. 8. The oscillator operates from 3.3 V, and
LASKIN et al.: 165-GHZ TRANSCEIVER IN SIGE TECHNOLOGY 1091 Fig. 9. Down-converter mixer schematic. consumes a total of 70 mA. To the best of our knowledge, this is the first quadrature oscillator at 80 GHz and the first differential oscillator at 160 GHz designed in a SiGe HBT technology. B. 160-GHz Gilbert-Cell Down-Convert Mixer A double-balanced Gilbert cell topology [22] mixer with on-chip RF and LO baluns is employed in the receiver. Its schematic is shown in Fig. 9. The baluns, described in detail in the next section, perform single-ended to differential conversion. The bias for the RF diff-pair and for the LO quad is applied to the center tap of the secondary coil of each transformer. Inductors are used instead of a current source to achieve larger voltage headroom, better linearity, and help to match the RF input to 50 at 160 GHz. Series 36-pH inductors are inserted between the collectors of the RF pair transistors and the emitters of the mixing quad to suppress the second harmonic (320 GHz) of the RF and LO signals over a broad band. The reactance of the LO and RF inputs is tuned out by employing shunt capacitors and series inductive transmission lines, which are part of the interconnect. The mixer schematic includes several inductors that model every piece of interconnect line in the mixer. Lines over the silicon substrate are modeled using the inductor 2- model, while interconnect that passes over metal is described as transmission lines. Furthermore, all metal-to-metal overlap capacitances are extracted using ASITIC and are included in the simulation schematic. They are not shown here for clarity. There is no IF amplifier at the mixer output. Instead, the differential IF output is matched to 50 at each side over a broad bandwidth (DC to 10 GHz) with the help of a network of inductors, capacitors ( and ) and on-chip 50- resistors. A Fig. 10. Layout snapshot of the down-converter mixer. broad IF bandwidth is required for communications at data rates above 10 Gb/s and for applications such as radio astronomy and imaging. In each IF matching network two identical inductors, , are employed instead of a single large inductor, to increase the self-resonance frequency of those inductors beyond 50 GHz. Shunt capacitors tune the impedance to 50 . The mixer layout (illustrated in Fig. 10) is fully symmetric with respect to the LO-to-RF line. Symmetry is essential for proper double-balanced mixing operation, for impedance matching, and for achieving high isolation at mm-wave frequencies. The mixer operates from 3.3 V and consumes 15 mA. All transistors have the same size ( m, m) and are biased at the peakcurrent density of 14 mA/ m . Thanks to its balanced multiplier structure, this mixer works up to a record 180 GHz.
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