clevo m860tu.pdf - tim.id.au

Clock Generator
CLOCK GENERATOR
2
Layout note:
PLACE CRYSTAL WITHIN 500
MILS OF ICS9LPR363
X4
* 1 4. 3 1 8M H z
2
1
X3
14.318181M20FAQ M Hz
2
1
C5 25
27p_N PO_04
38
22
PC LK_TPM
PC LK_KBC
36 R O B S O N _C LK R E Q #
23 3G_CLKREQ #
5 MC H_ CL KREQ #
C 5 40 *1 0p _ N P O _0 4
R 4 19
PC LK_ICH
R6 63
14 PCLK_ICH
C LK_ ICH 4 8 R4 21
15 CL K_IC H4 8
C LK_BSEL0 R422
C LK_BSEL1 R 4 17
C LK_BSEL2 R 4 11
C LK_ ICH 1 4 R4 13
15 CL K_IC H1 4
10 , 1 1 , 15 IC H_SMBD AT0
10 , 1 1 , 15 IC H_SMBC LK0
3. 3 V M _C LK R405 10K_04
15 C LK_PW R GD
R4 0 2
*10m il_short
SE L27
_S RC1 27 _Se le ct Pi n23 Pin26
(p in6 6) (p in1 6) Pi n24 Pin27
10 K _ 04 CLK_ITP_EN 17
22 _ 04 DVT
33 _ 04 PVT
2.2K_04
F SLA 21
DVT
10 K _ 04
F SLB 14
10 K _ 04
F SLC 8
33 _ 04
PVT
9
10
C LK _PW R GD _T 1
C5 2 0
*0 .1 u_ X 7 R_ 04
PCI_ F5 /ITP_EN
USB_ 4 8M Hz /FSLA
FSLB/PCI2
REF0 /FSL C
SDATA
SCLK
CK_ PW RG D/PD #
46
SRC T6_LPR/CR #_J
45
SRC C6 _ LPR /CR #_ I
43
SRC T5_LPR 44
SR CC5_LPR
41
SRC T4_LPR 42
SR CC4_LPR
38
SRC T3_LPR 39
SR CC3_LPR
36
SR CT2_ L PR/C R# _ G
37
S RCC 2_ L PR/C R# _ H
26
27MHz_NonSS/SRCT1/LCD-SST_LPR 27
27MH z_SS/SR CC1/LCD -SSC_LPR
23
SRCT0_LPR /DOTT_96_LPR 24
SR CC0_LPR/DOTC_96_LPR 32
SATAT_LPR 33
SATAC_LPR
IC S9LPR S395BKLFT
C L K_C RJ #
Z1823
4
CLK_ PCIE_ 3G
CLK_ PCIE_ 3G# 3
CLK_ PCIE_ CR 4
3
CLK_ PCIE_ CR#
Z1831
Z1832 4
Z1833 3
Z1834 4
Z1835 3
CLK_ SATA 4
3
CLK_ SATA#
R691 475_1%_04
R151 475_1%_04
1 RN1 0
2 *4P2RX0_04 1 RN1 2
2 *4P2RX0_04 R420 475_1%_04
1 RN1 4
2 *4P2RX0_04 1 RN1 3
2 *4P2RX0_04 1 RN1 5
CLK_SATA
2 *4P2RX0_04 CLK_SATA#
GLAN_CLKREQ # 19
WLAN_CLKREQ # 36
CLK_PCIE_3G 23
CLK_PCIE_3G# 23
CLK_PCIE_RO BSON 36
CLK_PCIE_RO BSON # 36
CLK_PCIE_CR 20
CLK_PCIE_CR # 20
NEW C ARD _C LKREQ# 21
CL K_ DR EF_SS 5
CL K_ DR EF_SS # 5
CL K_ DR EF 5
CL K_ DR EF# 5
CLK_SATA 13
CLK_SATA# 13
Layout note:
C LK_ PC IE_3 GPL L
C LK_ PC IE_3 GPL L #
C LK_ ICH 4 8
PC LK_KBC
PC LK_IC H
C LK _ P C I E _G LA N
C LK _ P C I E _G LA N #
C LK_ PC IE_M XM
C LK_ PC IE_M XM #
C LK_DR EF
C LK_DR EF#
C LK_DR EF_SS
C 5 05
C 5 06
C 5 41
C 5 39
C 5 37
C 5 19
C 5 15
C 5 07
C 5 08
C 5 42
C 5 43
C 5 44
*1 0p _ N P O _0 4
*1 0p _ N P O _0 4
*1 0p _ N P O _0 4
*1 0p _ N P O _0 4
*1 0p _ N P O _0 4
*1 0p _ N P O _0 4
*1 0p _ N P O _0 4
*1 0p _ N P O _0 4
*1 0p _ N P O _0 4
*1 0p _ N P O _0 4
*1 0p _ N P O _0 4
*1 0p _ N P O _0 4
0
0
0
1
SR C0
DO T96
27 FI X/S S
LC DS S
3. 3 V M
Place terminationclose to
ICS9LPR395
C LK_DR EF_SS# C 5 45 *1 0p _ N P O _0 4
1
0 SRC 0 SRC1
R140 10K_04 MC H_ CL KREQ #
PVT CL K_D REF
CL K_D REF#
4
3
5
6
1
1 DO T96 SR C1
CL K_D REF_ SS 2
CLK_D REF_SS# 1
7
8
CP U_BSEL0
C5 2 2
27p_NPO_04 1.05VS
R 40 0
*56_04
R 1 33 *1 0m i l _s h or t
R 39 9
1K_04
XT A L _I N
XT A L _O U T
BSE L2 BS EL1 BS EL 0
Ho st Cl oc k
Fr eq uen cy
0 0 1 533 MHz
0 1 1 667 MHz
0 1 0 800 MHz
0 0 0 10 66 MH z
15 PM _STPC PU#
15 PM_STPP CI#
PC LK_KBC
3.3VM _C LK
C LK_BSEL0
R 13 2
1K_04
PM _STPCP U#
PM _STPPC I#
PVT: for ETPM
R 6 92 *3 3_ 0 4
R4 16 22 _ 04
R 1 44 *1 0m i l _s h or t
5
4
X1
X2
65
40 CPU _STO P#
PCI_STOP#
11
Z 18 0 2 13
15
PCI0 /CR # _C
PCI1 /CR # _D
PCI3
2
CR #_A 7
19 CR #_B 31 CR #_E CR #_F CL K_ CRM # 60
CR #_M 2
C PU_BSEL1
CR# A:
CR# B:
CR# C:
CR# D:
CR# E:
R 4 18 10 K _ 04 CL K_ 27 _ SEL 16
PCI4 /2 7_ Se lec t
R 1 45 10 K _ 04 CLK_SEL27 66
SEL27_SRC 1/R ESET#
M CH _BSEL0 5
SGN D
73
R1 34
* 10 m il_ s ho rt
34
6
12
20
25
29
54
72
VDD A
VD DRE F
VDD PCI
VD D48
VDD
VDD SRC 0
VD DSR C1
VDD CPU
GN DREF
G NDPC I
GND 4 8
GN D
GND SRC 0
GN DA
G ND SRC1
GN DSRC 2
G NDC PU
3
18
22
28
30
35
47
57
69
1. 0 5 V S
R3 98
1K _ 0 4
R 39 7
*0 _ 0 4
C2 4 1
C 21 5
C2 2 9
C 2 42
C2 4 3
C2 44
C2 1 1
C5 49
0.1u_10V_04 0.1u_10V_04 0.1u_10V_04 0.1u_10V_04 0.1u_10V_04 0.1u_10V_04 0.1u_10V_04 0.1u_10V_04
U2 6
CP UT1_ L PR_ F
C PUC 1_ L PR_ F
CPU T0_LPR
C PUC0_LPR
C PUT2_ITP/SR CT13_LPR
CPU C2 _ ITP/SR CC 13_ L PR
C LK_BSEL1
R1 35
1K _ 0 4
40 m il
SR CT12_LPR
SR CC 12_LPR
SR CT11_LPR/CR #_L
SR CC11_LPR /CR #_K
SR CT10_LPR
SR CC 10_LPR
SRC T9_LPR
SR CC9_LPR
SRC T8_LPR
SR CC8_LPR
SRC T7_LPR
SR CC7_LPR
68
67
71
70
64
63
62
61
59
58
56
55
52
53
50
51
48
49
MCH _BSEL1 5
3.3VM_CLK
CLK_MCH_BCLK 1
2 CLK_MCH_BCLK#
4 RN3
CL K_ MC H_ BCL K
3 *4P2RX0_04 CL K_ MC H_ BCL K#
CLK_CPU_BCLK 1 4 RN2
CL K_ CPU _ BCL K
CLK_CPU_BCLK# 2 3 *4P2RX0_04 CL K_ CPU _ BCL K#
1 CLK_PCIE_3GPLL
CLK_PCIE_3GPLL# 2
4 RN4
CLK_PCIE _3GPLL
3 *4P2RX0_04 CLK_PCIE _3GPLL#
CLK_PCIE_MXM 1 4 RN5
CLK_PCIE _M XM
CLK_PCIE_MXM# 2 3 *4P2RX0_04 CLK_PCIE _M XM #
C L K_C RL #
CLK_PCIE_ICH
CLK_PCIE_ICH#
1
2
4 RN6
3 *4P2RX0_04 4
CLK_PCIE_GLAN
CLK_PCIE_GLAN# 3
1 RN7
2 *4P2RX0_04 CLK_PCIE_WLAN 4
CLK_PCIE_WLAN# 3
CLK_PCIE_NEW_CARD 4
3
CLK_PCIE_NEW_CARD#
2
CPU_ BSEL 2
R690 475_1%_04
R1 3 7
*1 0m i l_ s h ort
CLK_PCIE _IC H
CLK_PCIE _IC H#
CLK_PCIE _G LAN
CLK_PCIE _G LAN #
R3 9 6
*1 K _ 0 4
R3 95
1K_04
CL K_BSE L2
R1 3 6
1K_04
CL K_ MC H_ BCL K 4
CL K_ MC H_ BCL K# 4
CL K_ CPU _BC L K 2
CL K_ CPU _BC L K# 2
CLK_PCIE_3GPLL 5
CLK_PCIE_3GPLL# 5
CLK_PCIE_MXM 37
CLK_PCIE_MXM # 37
MXM_CLKREQ # 37
CLK_PCIE_ICH 14
CLK_PCIE_ICH # 14
CLK_PCIE_GLAN 19
CLK_PCIE_GLAN # 19
3.3VM
1 RN8
2 *4P2RX0_04 CLK_PCIE_W LAN 36
CLK_PCIE_W LAN# 36
1 RN9
CLK_PCIE _N EW _C ARD
2 *4P2RX0_04 CLK_PCIE _N EW _C ARD #
C LK_PC IE_N EW _CARD 21
C LK_PC IE_N EW _CARD # 21
1.05VS
L47
C LK_ MC H_ BCL K
C LK_ MC H_ BCL K#
H CB2012KF-500T40
C LK_ ICH 1 4
C 5 50
C5 5 3
C5 52
C2 2 0
C5 51
C 54 8
10u_10V_08 10 u _1 0 V _ 08 10u_10V_08 1u _ 6 . 3V _ 0 4 1u_6.3V_04 1u _ 6 . 3V _ 0 4
C LK_ PC IE_IC H
C LK_ PC IE_IC H#
C LK_ SAT A
C LK_ SAT A#
C LK_ PC IE_3 G
C LK_ PC IE_3 G#
CLK_PCIE_WLAN#
CL K_ PCIE_ CR #
CLK_PCIE_RO BSON
CLK_PCIE_RO BSON #
C 5 03 *1 0p _ N P O _0 4
C 5 09 *1 0p _ N P O _0 4
C 5 46 *1 0p _ N P O _0 4
C 5 47 *1 0p _ N P O _0 4
C 5 29 *1 0p _ N P O _0 4
C 5 23 *1 0p _ N P O _0 4
C 5 21 *1 0p _ N P O _0 4
C 5 38 *1 0p _ N P O _0 4
C 5 35 *1 0p _ N P O _0 4
CLK_PCIE_NEW _C ARD C 5 26 *1 0p _ N P O _0 4
CLK_PCIE_NEW _C ARD# C 5 24 *1 0p _ N P O _0 4
R N24 8P4RX0_04
C 5 04 *1 0p _ N P O _0 4
C 5 32 *1 0p _ N P O _0 4
C 5 10 *1 0p _ N P O _0 4
C 5 30 *1 0p _ N P O _0 4
C 5 33 *1 0p _ N P O _0 4
10,11,14,15,16,32 3.3VM
2,3,5,9,12,13,14,15,16,19,20,21,22,23,24,25,26,28,30,32,33,35,36,37,38 3.3VS
2,3,4,5,9,13,16,331.05VS
MC H_BSEL2 5
CLK_PCIE_WLAN
CL K_ PCIE_ CR
Schematic Diagrams
Sheet 18 of 42
Clock Generator
Clock Generator B - 19
B.Schematic Diagrams