DATA SHEET - IEETA

More documents

Recommendations

Info

Philips Semiconductors Product specification 8-bit microcontroller with on-chip CAN P8xC592 handbook, full pagewidth I N T E R N A L B U S Fig.9 Functional diagram of Pulse Width Modulated outputs. 1996 Jun 27 18 f clk PWMP 10 ANALOG-TO-DIGITAL CONVERTER (ADC) PRESCALER 8-BIT COUNTER The analog input circuitry consists of an 8-input analog multiplexer and an ADC with 10-bit resolution. The analog reference voltage and analog power supplies are connected via separate input pins. The conversion takes 50 machine cycles i.e. 37.5 μs at 16 MHz oscillator frequency. The input voltage swing is from 0 V to AVDD. The ADC is controlled using the ADCON control register. Register bits ADCON.0 to ADCON.2 select the input channels of the analog multiplexer (see Fig.10). The completion of the 10-bit analog-to-digital conversion is flagged by ADCI in the ADCON register and the result is stored in the SFR ADCH (upper 8-bits) and the 2 lower bits (ADC.1 and ADC.0) in register ADCON. An analog-to-digital conversion in progress is unaffected by an external or software ADC start. The result of a completed conversion remains unchanged provided ADCI = HIGH. While ADCI or ADCS are HIGH, a new ADC START will be blocked and consequently lost. An analog-to-digital conversion already in progress is aborted when the Idle or Power-down mode is entered. 1/2 PWM0 8-BIT COMPARATOR 8-BIT COMPARATOR PWM1 OUTPUT BUFFER OUTPUT BUFFER PWM0 PWM1 MGA154 The result of a completed conversion (ADCI = HIGH) remains unaffected during the Idle mode. The LOW-to-HIGH transition of STADC is recognized at the end of a machine cycle and the conversion commences at the beginning of the next cycle. When a conversion is initiated by software, the conversion starts at the beginning of the machine cycle following the instruction that sets ADCS. The next two machine cycles are used to initiate the converter. At the end of this first cycle, the ADCS status flag is set to HIGH while the conversion is in progress. Sampling of the analog input commences at the end of the second cycle. During the next eight machine cycles, the voltage at the previously selected pin of Port 5 is sampled and this input voltage should be stable in order to obtain a useful sample. In any case, the input voltage slew rate must be less than 10 V/ms (5 V conversion range) in order to prevent an undefined result. The conversion takes four machine cycles per bit.
Philips Semiconductors Product specification 8-bit microcontroller with on-chip CAN P8xC592 10.1 ADC Control register (ADCON) Table 13 ADC Control register (address C5H) 7 6 5 4 3 2 1 0 ADC.1 ADC.0 ADEX ADCI ADCS AADR2 AADR1 AADR0 Table 14 Description of the ADCON bits BIT SYMBOL FUNCTION 7 ADC.1 Bit 1 of ADC converted value. 6 ADC.0 Bit 0 of ADC converted value. 5 ADEX Enable external start of conversion by STADC. If ADEX is: LOW, then conversion cannot be started externally by STADC (only by software by setting ADCS) HIGH, then conversion can be started externally by a rising edge on STADC or externally. 4 ADCI ADC interrupt flag. This flag is set when an analog-to-digital conversion result is ready to be read. If enabled, an interrupt is invoked. The flag must be cleared by software. It cannot be set by software (see Table 15). 3 ADCS ADC start and status. Setting this bit starts an analog-to-digital conversion. It may be set by software or by the external signal STADC. The ADC logic ensures that this signal is HIGH while the ADC is busy. On completion of the conversion, ADCS is reset at the same time the interrupt flag ADCI is set. ADCS can not be reset by software (see Table 15). 2 AADR2 Analog input select. This binary coded address selects one of the eight analog port pins of P5 to be 1 0 AADR1 AADR0 input to the converter. It can only be changed when ADCI and ADCS are both LOW. AADR2 is the MSB. (e.g. 100B selects the analog input channel ADC4) Table 15 ADCI and ADCS operating modes If ADCI is cleared by software while ADCS is set at the same time a new analog-to-digital conversion with the same channel-number may be started. It is recommended to reset ADCI before ADCS is set. ADCI ADCS OPERATION 0 0 ADC not busy, a conversion can be started. 0 1 ADC busy, start of a new conversion is blocked. 1 X (don’t care) Conversion completed; see note 1. Note 1. Start of a new conversion requires ADCI = 0. 1996 Jun 27 19
Page 1 and 2: DATA SHEET Product specification Su
Page 3 and 4: Philips Semiconductors Product spec
Page 17: Philips Semiconductors Product spec
Page 69 and 70:
Philips Semiconductors Product spec
Page 71 and 72:
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101 and 102:
Page 103 and 104:
Page 105 and 106:
Page 107 and 108:
show all

DATA SHEET - IEETA

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?