DATA SHEET - IEETA

More documents

Recommendations

Info

Philips Semiconductors Product specification 8-bit microcontroller with on-chip CAN P8xC592 13.3 Interface between CPU and CAN The internal interface between the P8xC592's CPU and on-chip CAN-controller is achieved via the following four SFRs (see Fig.13): • CANADR, to point to a register of the CAN-controller • CANDAT, to read or write data • CANCON, to read interrupt flags and to write commands • CANSTA, to read status information and to write DMA pointer. Additionally, the DMA-logic allows a high-speed data exchange between the CAN-controller and the CPU's on-chip MAIN RAM. For more information, see Section 13.5.15 “Handling of the CPU-CAN interface”. 13.4 Hardware blocks of the CAN-controller The P8xC592 CAN-controller contains all necessary hardware for high performance serial network communications (see Fig.14 and Table 29). handbook, full pagewidth CPU MAIN RAM internal bus 4 special function registers DMA bus 1996 Jun 27 28 It controls the communication flow through the area network using the CAN-protocol. The CAN-controller meets the following automotive requirements: • Short message length • Bus access priority, determined by the message identifier • Powerful error handling capability • Configuration flexibility to allow area network expansion • Guaranteed latency time for urgent messages; – The latency time defines the period between the initiation (Transmission Request) and the start of the transmission on the bus. The latency time strongly depends on a large variety of bus-related conditions. In the case of a message being transmitted on the bus and one distortion, the latency time can be up to 149 bit times (worst case). For more information see Chapter 22 “CAN application information”. DBH CANADR DAH CANDAT D9H CANCON CANSTA D8H DMA LOGIC Fig.13 Interface between CPU and CAN-controller. ADDRESS <strong>DATA</strong> CAN CONTROLLER MGA158
Philips Semiconductors Product specification 8-bit microcontroller with on-chip CAN P8xC592 handbook, full pagewidth address data INTERFACE MANAGEMENT LOGIC TRANSMIT BUFFER ON - CHIP RECEIVE BUFFER 0 RECEIVE BUFFER 1 Fig.14 Block diagram of the P8xC592 on-chip CAN-controller. Table 29 Hardware blocks of the CAN-controller (see Fig.14) NAME BLOCK DESCRIPTION Interface Management Logic IML Interprets commands from the CPU, allocates the message buffers (TBF, RBF0 and RBF1) and provides interrupts and status information to the microcontroller. Transmit Buffer TBF 10 bytes memory into which the CPU writes messages which are to be transmitted over the CAN network. Receive Buffers (0 and 1) RBF0 RBF0 and RBF1 are each 10 bytes memories which are alternatively used to RBF1 store messages received from the CAN network. The CPU can process one message while another is being received. Bit Stream Processor BSP Is a sequencer, controlling the data stream between the Transmit Buffer, Receive Buffers (parallel data) and the CAN-bus (serial data). Bit Timing Logic BTL Synchronizes the CAN-controller to the bitstream on the CAN-bus. Transceiver Control Logic TCL Controls the output driver. Error Management Logic EML Performs the error confinement according to the CAN-protocol. 1996 Jun 27 29 BIT TIMING LOGIC TRANSCEIVER LOGIC CAN CONTROLLER ERROR MANAGEMENT LOGIC BIT STREAM PROCESSOR 2 2 MGA159 CRX0 and CRX1 CTX0 and CTX1
Page 1 and 2: DATA SHEET Product specification Su
Page 3 and 4: Philips Semiconductors Product spec
Page 27: Philips Semiconductors Product spec
Page 79 and 80:
Philips Semiconductors Product spec
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101 and 102:
Page 103 and 104:
Page 105 and 106:
Page 107 and 108:
show all

DATA SHEET - IEETA

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?