DATA SHEET - IEETA

Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
13.5.10 BUS TIMING REGISTER 1(BTR1)
The contents of Bus Timing Register 1 defines the length
of the bit period, the location of the sample point and the
number of samples to be taken at each sample point.
Table 47 Bus Timing Register 1 (address 7)
Table 48 Description of the BTR1 bits
1996 Jun 27 43
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).For further information
on bus timing, see Sections 13.5.9 and 13.5.18.
7 6 5 4 3 2 1 0
SAM TSEG2.2 TSEG2.1 TSEG2.0 TSEG1.3 TSEG1.2 TSEG1.1 TSEG1.0
BIT SYMBOL FUNCTION
7 SAM Sampling. If the bit SAM is:
HIGH (3 samples), then three samples are taken. This is recommended for slow/medium speed
buses (SAE class A and B) where filtering of spikes on the bus-line is beneficial
(see Section 13.5.19.6)
LOW (1 sample), the bus is sampled once.
This is recommended for high speed buses (SAE class C).
6 TSEG2.2 Time Segment 1 (TSEG1) and Time Segment 2 (TSEG2).
5 TSEG2.1 TSEG1 determines the number of clock cycles per bit period and the location of the sample point
4 TSEG2.0 tTSEG1 = tSCL ( 8TSEG1.3 + 4TSEG1.2 + 2TSEG1.1 + TSEG1.0 + 1)
.
3 TSEG1.3
TSEG2 determines the number of clock cycles per bit period and the location of the sample point:
2
1
TSEG1.2
TSEG1.1
tTSEG2 =
tSCL ( 4TSEG2.2 + 2TSEG2.1 + TSEG2.0 + 1)
.
0 TSEG1.0