DATA SHEET - IEETA
DATA SHEET - IEETA
DATA SHEET - IEETA
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Philips Semiconductors Product specification<br />
8-bit microcontroller with on-chip CAN P8xC592<br />
14 INTERRUPT SYSTEM<br />
External events and the real-time-driven on-chip<br />
peripherals require service by the CPU asynchronous to<br />
the execution of any particular section of code. To tie the<br />
asynchronous activities of these functions to normal<br />
program execution a multiple-source, two-priority-level,<br />
nested interrupt system is provided. Interrupt response<br />
latency is from 2.25 μs to7.5μs when using a 16 MHz<br />
crystal. The latency time strongly depends on the<br />
sequence of instructions executed directly after an<br />
interrupt request. During a CAN-DMA transfer the interrupt<br />
system is disabled (see Section 13.5.17). The P8xC592<br />
acknowledges interrupt requests from fifteen sources as<br />
follows:<br />
• INT0 and INT1: externally via pins 27 and 28<br />
respectively<br />
• Timer 0 and Timer 1: from the two internal counters<br />
– If the capture function remains unused and the<br />
Capture Register contents are ‘don't care’ then the<br />
corresponding input pins ‘CTnI’, with ‘n = 0 ... 3’, may<br />
be used as positive and/or negative edge triggered<br />
external interrupts INT2 to INT5. But note that they<br />
can not terminate the Idle mode because the Timer 2<br />
is switched off then<br />
• Timer T2, 8 separate interrupts:<br />
– 4 capture interrupts<br />
– 3 compare interrupts<br />
– an overflow interrupt<br />
• ADC end-of-conversion interrupt<br />
• CAN-controller interrupt<br />
• UART serial I/O port interrupt.<br />
Each interrupt vectors to a separate location in Program<br />
Memory for its service program. Each source can be<br />
individually enabled or disabled by a corresponding bit in<br />
the IEN0 or IEN1 register, moreover each interrupt may be<br />
programmed to a HIGH or LOW priority level using a<br />
corresponding bit in the IP0 or IP1 register. Also all<br />
enabled sources can be globally disabled or enabled. Both<br />
external interrupts can be programmed to be<br />
level-activated or transition-activated, and an active LOW<br />
level allows ‘wire-ORing’ of several interrupt sources to the<br />
input pin.<br />
1996 Jun 27 63