DATA SHEET - IEETA
DATA SHEET - IEETA
DATA SHEET - IEETA
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Philips Semiconductors Product specification<br />
8-bit microcontroller with on-chip CAN P8xC592<br />
Table 1 Pin description for single function pins (SOT188-2; see note 1)<br />
SYMBOL PIN DESCRIPTION<br />
VDD 2 Power supply, digital part (+5 V). For normal operation and power reduced modes.<br />
STADC 3 Start ADC operation. Input starting analog-to-digital conversion (note 2). This pin must not float.<br />
PWM0 4 Pulse width modulation output 0.<br />
PMW1 5 Pulse width modulation output 1.<br />
EW 6 Enable Watchdog Timer (WDT): enable for T3 Watchdog Timer and disable Power-down mode.<br />
This pin must not float.<br />
RST 15 Reset: input to reset the P8xC592 (note 3).<br />
CVSS 22 CAN ground potential for the CAN transmitter outputs.<br />
XTAL2 33 Crystal pin 2: output of the inverting amplifier that forms the oscillator.<br />
When an external clock oscillator is used this pin is left open-circuit.<br />
XTAL1 34 Crystal pin 1: input to the inverting amplifier that forms the oscillator, and input to the internal clock<br />
generator. Receives the external clock oscillator signal, when an external oscillator is used.<br />
VSS 35 Ground, digital part.<br />
PSEN 44 Program Store Enable: Read strobe to external Program Memory (active LOW).<br />
Drive: 8 × LSTTL inputs.<br />
ALE 45 Address Latch Enable: latches the Low-byte of the address during accesses to external memory<br />
(note 4). Drive: 8 × LSTTL inputs; handles CMOS inputs without an external pull-up.<br />
EA 46 External Access input. See note 5.<br />
REF 55 1 ⁄2AVDD reference voltage output respectively input (note 6).<br />
CRX1 56 Inputs from the CAN-bus line to the differential input comparator of the on-chip CAN-controller<br />
CRX0 57 (note 7).<br />
AVREF− 58 Low-end of ADC (analog-to-digital) conversion reference resistor.<br />
AVREF+ 59 High-end of ADC (analog-to-digital) conversion reference resistor (note 8).<br />
AVSS 60 Ground, analog part. For ADC, CAN receiver and reference voltage.<br />
AVDD 61 Power supply, analog part (+5 V). For ADC, CAN receiver and reference voltage.<br />
Notes<br />
1. To avoid a ‘latch up’ effect at power-on: VSS − 0.5 V < ‘voltage on any pin at any time’ < VDD + 0.5 V.<br />
2. Triggered by a rising edge. ADC operation can also be started by software.<br />
3. RST also provides a reset pulse as output when timer T3 overflows or after a CAN wake-up from Power-down.<br />
4. ALE is activated every six oscillator periods. During an external data memory access one ALE pulse is skipped.<br />
5. See Section 7.1, Table 3 for EA operation. For P83Cxxx microcontrollers specified with the option ‘ROM-code<br />
protection’, the EA pin is latched during reset and is ‘don't care’ after reset, regardless of whether the ROM-code<br />
protection is selected or not.<br />
1996 Jun 27 7